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Prof. Christian Piguet , CSEM

Theme: Leakage and Total Power Reduction at Architectural Level
Date: mardi 15 juin 2004, de 9h00 à 12h00, Institut National Polytechnique de Grenoble, Salle T312, Entrée T,


Christian Piguet received the M. S. and Ph. D. degrees in electrical engineering from the Ecole Polytechnique Fédérale de Lausanne, respectively in 1974 and 1981. He joined the Centre Electronique Horloger S.A., Neuchâtel, Switzerland, in 1974. He is now Head of the Ultra Low Power Circuits section at the CSEM Centre Suisse d'Electronique et de Microtechnique S.A. He is presently involved in the design of low-power low-voltage integrated circuits in CMOS technology, including design methodologies, microprocessor architectures and logic design. He is Professor at the Ecole Polytechnique Fédérale Lausanne (EPFL), Switzerland, lectures in VLSI and microprocessor design at the University of Neuchâtel, Switzerland and in the ALaRI Master at the University of Lugano, Switzerland. He is also a lecturer for many postgraduates courses in low-power design. Christian Piguet holds about 30 patents in digital design, microprocessors and watch systems. He is author and co-author of more than 150 publications in technical journals and of books and book chapters in low-power digital design. He has served as reviewer for many technical journals. He also served as Guest Editor for the July 96 JSSC Issue TVLSI Feb. and March 2004 issues. He is member of steering and program committees of numerous conferences and has served as Program Chairman of PATMOS'95 in Oldenburg, Germany, co-chairman at FTFC'99 in Paris, Chairman of the ACiD'2001 Workshop in Neuchâtel, Program Co-Chair of VLSI-SOC 2001 in Montpellier and Program Co-Chair of ISLPED 2002 in Monterey. He was Chairman of the PATMOS executive committee during 2002. He was Low-Power Topic Chair at DATE 2004. (for further information please see:


As leakage power and total power is a more and more dramatic issue is very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and VT that define the optimal total power consumption of each architecture.