Coopération

Séminaires


< retour aux séminaires

Prof. Saeyang YANG, SEVITS Technology Inc., Pusan, Korea (http://www.sevits.com)

Theme: Simulation + Emulation : A New Hope in Verification Crisis ?
Date: 26 October 2000

Biography

B.S., Korea University, 1981 M.S., Korea University, 1985 Ph.D., University of Massachusetts, 1990 Saeyang Yang joined the Dept. of Computer Engineering, Pusan National University, Korea in 1991, where he is now an Associate Professor. Before joining the department, he worked as a Senior Member of Technical Staff at Microelectronics Center of North Carolina (MCNC), USA. His current research interests include: design verification for SOC's, VLSI logic synthesis & testing, and dynamically reconfigurable FPGAs. He has published a number of papers in those areas to major journals and conferences, including IEEE Trans. on CAD, and Journal of The Korea Information Science Society (KISS). Recently, he has founded Sevits Technology, Inc., a startup specialized in HW-based design verification.

Abstract

In the crisis of soaring design complexity, most of the designers have realized that the simulation-only verification methods are no longer valid for achieving proper verification productivity. Therefore, a variety of new verification solutions has been introduced into the market. Notable among them are HW-assisted methods, which can be further divided into emulation and prototyping. Each of these methods has not only its own advantages, but also clear disadvantages over others. 1. Simulation (a) Good: very flexible, 100% visibility, short compile time, timing verification possible (b) Bad: very slow execution, no in-circuit capability 2. Emulation (a) Good: fast execution, in-circuit capability, large design capacity (b) Bad: very expensive, hard to use and learn, very long compile time, limited visibility, functional verification only 3. Prototyping (a) Good: ultra fast execution, in-circuit capability, moderate cost (b) Bad: long compile time, very limited visibility, functional verification only If a new verification solution could provide all the above advantages then a dramatic increase in the design verification productivity would be possible. Such a solution would have the following features: (a) Both functional and timing verification possible, (b) Very flexible, with 100% visibility, (c) Ultra fast execution, (d) Low cost, (e) In-circuit capability, and (f) Short compile time. In this talk, I will introduce an integrated verification technique that can provide all the above features. This could be possible with the verification bridge. The verification bridge is a new technology that can tightly combine any simulator with any of the emulators/prototypers in the open environment. I will describe how the concept of verification bridge can achieve all of these features, with already existing verification solutions, and show its benefits. Biography B.S., Korea University, 1981 M.S., Korea University, 1985 Ph.D., University of Massachusetts, 1990 Saeyang Yang joined the Dept. of Computer Engineering, Pusan National University, Korea in 1991, where he is now an Associate Professor. Before joining the department, he worked as a Senior Member of Technical Staff at Microelectronics Center of North Carolina (MCNC), USA. His current research interests include: design verification for SOC's, VLSI logic synthesis & testing, and dynamically reconfigurable FPGAs. He has published a number of papers in those areas to major journals and conferences, including IEEE Trans. on CAD, and Journal of The Korea Information Science Society (KISS). Recently, he has founded Sevits Technology, Inc., a startup specialized in HW-based design verification.