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Peter A. BEEREL, University of Southern California (USC) - SEMINAR CANCELLED

Theme: CANCELLED - Saving Power by Converting FF-based Designs to 3-Phase Latch Based Designs
Date: March 13th, 2020 - 14:00, Grenoble INP - Amphi Gosse


Peter A. BEEREL received his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1991 and 1994, respectively. He then joined the Ming Hsieh Department of Electrical and Computer Engineering at the University of Southern California where he is currently a Full Professor and the Associate Chair of the Computer Engineering Division. He is also a Research Director at the Information Science Institute at USC. Previously, he co-founded TimeLess Design Automation to commercialize an asynchronous ASIC flow in 2008 and sold the company in 2010 to Fulcrum Microsystems which was bought by Intel in 2011. He has published more than 130 papers and co-invented over 17 US patents. His interests include a variety of topics in computer-aided design, hardware security, machine learning, and asynchronous VLSI and the commercialization of these technologies. He is a Senior Member of the IEEE.



As Moore's law tapers off, ASIC designers are struggling to find new opportunities for energy savings. This talk argues that latch-based designs should be revisited, proposes new optimizations and design flows for latch-based designs, and discusses their applications from traditional synchronous design to asynchronous bundled-data as well as radiation-hardened design.

Most RTL specifications are flop-centric and automatic conversion of FF to latch-based designs is challenging. Most conventional flows convert the FF-based designs into pulsed-latch designs or two-phase latch-based designs controlled by either master-slave clocks or bundled-data asynchronous controllers. Pulsed-latch schemes are an intermediate approach that lies between latch and flip-flop based designs, however, are subject to hold problems and pulse width variations. Whereas two-phase designs are inherently more robust than pulsed-latch designs, this talk argues that multi-phase latch-based designs can often be an attractive alternative.

We will present an automated conversion flow that converts any synchronous RTL specification with a single clock domain to a target 3-phase synchronous latch-based design with reduced number of required latches, saving both register and clock-tree power. Post place-and-route results demonstrate that our 3-phase latch-based designs save an average of 20.8% and 23.7% power on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to their more traditional FF and master-slave based alternative.

We will then discuss how these results can be applied to both asynchronous bundled-data designs as well as related SEU-resilient design. In asynchronous bundled-data design, the clocks are replaced with asynchronous handshake controllers that have the potential of better performance, lower power consumption, better modularity in large systems, and higher tolerance to PVT variations. We will first show how our efficient 3-phase synchronous latch-based designs can be easily transformed into bundled-data asynchronous design and then show how these bundled-data designs can be further enhanced to mitigate Single Event Transient (SETs) and upsets (SEUs) using a combination of temporal and spatial redundancy.