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Luca FRONTINI, University of Milan

Theme: Design of low-power associative memory cells in CMOS, and new synthesis techniques for lattices
Date: 08/03/2018 - 15:00, TIMA Laboratory - Room T312

Biography

Luca FRONTINI is a 3rd-year PhD student from the University of Milan.

Abstract

The trend in new electronic ICs is driven by a reduction of area occupation and power consumption. Today the scaled CMOS technologies are the main solution for digital processing. Therefore, a straightforward approach consists in reducing area and power of conventional CMOS. Meanwhile, new emerging technologies are being investigated, as they could replace CMOS in the future. CMOS transistor dimensions have been scaled for decades in an almost regular way, according to the Moore's law. However, the interconnection scaling is not optimal, as interconnections do not scale as well as transistors. Therefore, the number of metal layer has been increased, to exploit the vertical direction. The drawback is that the reduction of the minimum distance between interconnections increases the parasitic capacitance and consequently the dynamic power consumption. A new design of CMOS Associative Memory (AM) is presented. The approach aims at reducing dynamic power consumption. The new AM cells are used in High Energy Physics experiments to perform the track detection with a dedicate IC. The AMs find correlations between the input data (coming form the detector) and the pre-stored data. Being the data compared in parallel, a synchronous chip has a very peaked power consumption, with peaks aligned with the rising edge of the clock. For this reason, we need to optimize power consumption. Then, a new emerging technology based on nanocrossbars will be presented, and logic function implementation will be discussed. Nanocrossbars arrays are a novel nanotechnology based on molecular-scale self-assembled systems that consists of regular structures. Logic functions are obtained with arrays of crossbar-type switches. This structure is expected to reduce device dimensions and interconnection complexity with respect to CMOS.