< retour aux séminaires

Prof. Jiang Xu, Mobile Computing System Lab
Electronic and Computer Engineering
Hong Kong University of Science and Technology

Theme: Sensor Network on Chip: A HW-SW Collaborated Method for Resilient MPSoC
Date: 4th July : 10:30 am, room T-312, TIMA Laboratory


Jiang Xu received his Ph.D. degree from Princeton University. From 2001 to 2002, he worked at Bell Labs, NJ, as a Research Associate and discovered the First Generation Dilemma in platform-based SoC design methodologies. He was a Research Associate at NEC Laboratories America, NJ, from 2003 to 2005 and working on Network-on-Chip designs and implementations. He joined a startup company, Sandbridge Technologies, NY, from 2005 to 2007 and worked on the development and implementation of two generations of NoC-based ultra-low power Multiprocessor Systems-on-Chip for mobile platforms. Dr. Xu established Mobile Computing System Lab and Xilinx-HKUST Joint Lab at the Hong Kong University of Science and Technology. He currently serves as the Area Editor of NoC, SoC, and GPU for ACM Transactions on Embedded Computing Systems and Associate Editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He served on the steering committees, organizing committees, and technical program committees of many international conferences, including ICCAD, CASES, ICCD, EMSOFT, CODES+ISSS, NOCS, RTCSA, ASP-DAC, etc. Dr. Xu is an ACM Distinguished Speaker and an IEEE Distinguished Lecturer. He authored and coauthored more than 80 book chapters and papers in peer-reviewed journals and international conferences. He and his students received Best Paper Award from IEEE Computer Society Annual Symposium on VLSI in 2009, and Best Poster Award from AMD Technical Forum and Exhibition in 2010. He coauthored a book titled Algorithms, Architecture and System-on-Chip Design for Wireless Applications (Cambridge University Press). His research areas include network-on-chip, multiprocessor system-on-chip, optical interconnect, embedded system, computer architecture, low-power VLSI design, and HW/SW codesign.


Multiprocessor system-on-chip (MPSoC) is an attractive platform for embedded applications with growing complexity, because integrating a system or a complex subsystem on a single chip provides better performance and energy efficiency and lower cost per function. As feature sizes and power supply voltages continually decrease, MPSoC is becoming more susceptible to various transient threats, such as soft error and power/ground noise. Traditional solutions introduce large area, power and performance overheads to MPSoC. As the scale and complexity of MPSoC continuously increase, a systematic approach that not only detects reliability threats but also mitigates such threats accordingly at run time could potentially offer better performance, scalability, and flexibility for MPSoC designs. This talk will present a systematic approach, sensor network on chip (SENoC), to collaboratively detect, report, and alleviate run-time transient threats in MPSoC. SENoC not only detects threats and shares related information among processing units, but also plans and coordinates the related reactions. To highlight the details of our idea, SENoC is used and explained in case studies.