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Luigi CARRO, Informatics Institute of Universidade Federal do Rio Grande do Sul (UFRGS)

Theme: A microarchitecture approach to fault tolerance against soft errors > From the reconfigurable fabric to the execution model - 2 talks
Date: September 3rd, 2012 (Monday) - 15:00, Laboratoire TIMA, salle T312

Biography

Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively.
From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group.

In 1996 he received the Dr. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil.
He is presently a full professor at the Applied Informatics Department at the Informatics Institute of UFRGS, in charge of Computer Architecture and Organization courses at the undergraduate levels.

He is also a member of the Graduation Program in Computer Science at UFRGS, where he is co-responsible for courses on Embedded Systems, Digital signal Processing, and VLSI Design.
His primary research interests include embedded systems design, validation, automation and test, fault tolerance for future technologies and rapid system prototyping.
He has advised more than 20 graduate students, and has published more than 150 technical papers on those topics.
He has authored the book Digital systems Design and Prototyping (2001-in Portuguese) and is the co-author of Fault-Tolerance Techniques for SRAM-based FPGAs (2006-Springer), Dynamic Reconfigurable Architectures and Transparent optimization Techniques (2010-Springer) and Adaptive Systems (Springer 2012).
In 2007 he received the prize FAPERGS - Researcher of the year in Computer Science.

His most updated resume is located in http://lattes.cnpq.br/8544491643812450.
For the latest news, please check http://www.inf.ufrgs.br/~carro

Abstract

Talk 1 - Fast Error Detection through Efficient Use of Hardwired Resources in FPGAs
Providing high reliability for FPGAs is a demanding task, as such devices may be subject to faults in the configuration bitstream, altering the specified function.
Traditional modular redundancy remains the most used technique, due to its high fault coverage and low performance overhead. When high avail-ability and strict real-time deadlines must be considered, however, a short mean time to repair also becomes crucial. The use of fine-grained modules can accelerate error detection, fault diagno-sis and bitstream correction, but with increased area costs. In this work, we propose the use of hardwired resources found in state-of-the-art FPGAs to provide fast and area efficient fine-grained error detection. Experimental results show an average speed up in error detection of 7.68 times with only 3.2% more area over-head, when compared to coarse-grained modular redundancy.
Radiation results also illustrate and validate the proposed fault injection method.

Talk 2 - The single program approach for fault tolerance
This talk introduces the Resilient Adaptive Algebraic Architecture, which is capable of adapting parallelism exploitation in a time-deterministic fashion to reduce power consumption, while meeting the existing real-time deadlines. Furthermore, the architecture provides low overhead error correction capabilities, through the use of algebraic properties of the operations it performs. We use two real-time industrial case studies to validate the architecture and to show how the adaptive exploitation works. Finally, we present the results of fault-injection campaigns to show the architecture resilience against soft-errors.