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Dr. V. Pavlidis, EPFL, Switzerland

Theme: Design and Test Issues of 3-D Clock Distribution Networks
Date: Thursday May 24th, 11h00, Laboratoire TIMA, salle T312


Vasilis Pavlidis received the M.Sc. and Ph.D. degrees from the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA, in 2003 and 2008, respectively. He is presently a post-doctoral with the Integrated Systems Laboratory, EPFL, Lausanne, Switzerland. His current research interests include the areas of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI. He is the co-creator of the “Rochester cube” and co-author of the book “Three dimensional integrated circuit design”.


Designing a low power and robust clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities and the more complex effect of process and power supply variations. A statistical model to accurately characterize these variations is discussed in this talk. Based on the investigation of different case studies, several design guidelines for 3-D clock networks are proposed. To reduce power – a crucial requisite in 3-D ICs – resonant clock networks are also considered. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In addition to design, test is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. By exploiting the resonance phenomena and inductive coupling, a potent approach to produce low-power and pre-bond testable (with negligible test area overhead) 3-D clock distribution networks is presented.