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Prof. George STAMOULIS, University of Thessaly (Greece)

Theme: Power integrity analysis in sub-20 nm designs
Date: Feb, 23rd 2012 (this Thursday) - 15:00, TIMA Laboratory, room T312

Biography

George Stamoulis graduated from the Electrical Engineering Department of the National Technical University of Athens in 1989.
He received his M.S. and Ph.D. degrees from the Electrical and Computer Engineering Department of the University of Illinois at Urbana-Champaign in 1991 and 1994 respectively.
After spending a year as a Visiting Assistant Professor at the University of Iowa, he joined Intel Corp. and focused on power estimation and optimization, as a Senior CAD Engineering (1995-1996), as group leader of the PowerCAD group (1996-1998), as manager of the Santa Clara division of the Strategic CAD Laboratories (1998-1999), and as leader of the power reduction effort of the Pentium M processor for the Centrino platform.
In 2001, he became an Assistant Professor at the Department of Electronics and Computer Engineering of the Technical University of Crete.
In 2003 he became an Associate Professor at the Department of Computer and Communications Engineering at the University of Thessaly, and in 2009 he became a Professor at the same department.
>From 2003 to 2007 he was the elected Associate Head of the Department and in 2007 he was elected Head.
He has authored more than 50 journal and conference papers and has received two US patents.
He is also the founder of two technology start-ups.
His research interests are in the area of average and maximum power estimation and optimization, estimation and optimization of voltage drop of integrated circuit power delivery networks, low power design techniques, and reliability analysis and optimization.
His research interests also include wireless sensor networks and hardware acceleration of image and video compression algorithms.

Abstract

As we move into the sub-20nm processes design methodologies add greater overhead to the designs while phenomena that were considered second-order force ever greater overdesign.
The net result is that designers do not get the most out of the advanced processes with a lot of performance and power being left on the table.
Furthermore, design effort is increasingly spent on methodology induced issues not on the real problems of the design.
The power integrity problem will be used as a testbed for exploring new design methodologies based on novel simulation and analysis approaches, and their consequences into the entire design flow, along with possible future directions.