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Prof. Shobha VASUDEVAN, University of Illinois, USA

Theme: GoldMine : Automatic assertion generation and achieving test coverage closure
Date: March 18th, 2011 (Friday), 11 h 00 - TIMA Laboratory, room N121


Shobha VASUDEVAN is an assistant professor of Computer Engineering in the ECE Department, at the University of Illinois. She obtained her PhD and MS degrees from the University of Texas at Austin.
Her research interests are in design verification, validation, reliability, software testing, data mining and formal verification. She is a recipient of the NSF CAREER award.


Assertions are ubiquitous in the modern system design cycle. They are used in pre-Silicon verification, post-Silicon validation and debug, emulation, reliability checking, and many related functional assurance phases. Assertion generation is an intensely manual, time-intensive task. GoldMine, developed by my group in UIUC, is an assertion generation software that uses a combination of data mining and static analysis of the design. GoldMine uses formal verification to guide the data mining algorithms. GoldMine assertions are attested by designers, as adding value to the verification process. In the first part of my talk, I will present the function and working of this engine. Counterexample feedback from formal verification of an assertion can be used to grow the size of the data set that is mined by GoldMine. When iteratively applied, this data set eventually captures the entire behavior. This data set now forms a test suite where coverage closure can be achieved. This algorithm for monotonically increasing coverage of validation inputs is presented in the second part of my talk. I will also briefly discuss how GoldMine can be applied in the context of soft error detection and emulation.