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183 résultats

  27 Revues internationales
   1 Brevets
  24 Conférences invitées
  84 Conférences internationales
   8 Chapitres de livre
   1 Livres & Éditions Ouvrages
   2 Revues nationales
   3 Conférences nationales
  14 Autres communications
   5 Logiciels
  14 Thèses

27 Revues internationales

 1 Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., Clocked and event-driven redundant adjustable precision computing, Microelectronics Reliability, Ed. Elsevier, Vol. 111, pp. 113729, DOI: 10.1016/j.microrel.2020.113729, août 2020
 
 2 Di Natale G., Bolchini C., Holding Conferences Online due to COVID-19: The DATE Experience, IEEE Design & Test, Ed. IEEE, Vol. 37, No. 3, pp. 116-118, DOI: 10.1109/MDAT.2020.2995140, juin 2020
 
 3 Fabero J.C., Mecha H., Franco F., Clemente J.A., Korkian G., Rey S., Cheymol B., Baylac M., Hubert G., Velazco R., Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 67, No. 7, pp. 1461-1469, DOI: 10.1109/TNS.2020.2977874, mars 2020
 
 4 Portolan M., Automated Testing Flow: the Present and the Future, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. , DOI: 10.1109/TCAD.2019.2961328, décembre 2019
 
 5 Galy P., De Conti L., Delahaye G., Anghel L., Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology, Microelectronics Reliability, Ed. Elsevier, Vol. , DOI: 10.1016/j.microrel.2019.06.069, septembre 2019
 
 6 Valea E., Da Silva M., Di Natale G., Flottes M.-L., Rouzeyre B., A Survey on Security Threats and Countermeasures in IEEE Test Standards, IEEE Design & Test, Ed. IEEE, Vol. 36, No. 3, pp. 95-116, DOI: 10.1109/MDAT.2019.2899064, juin 2019
 
 7 Vallero A., Savino A., Chatzidimitriou A., Kaliorakis M., Kooli M., Riera V., Di Natale G., Bosio A., Canal R., Gizopoulos D., Di Carlo S., Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems, IEEE Transactions on Computers, Ed. IEEE, Vol. 68, No. 5, pp. 765-783, DOI: 10.1109/TC.2018.2887225, mai 2019
 
 8 Valea E., Da Silva M., Flottes M.-L., Di Natale G., Rouzeyre B., Stream vs block ciphers for scan encryption, Microelectronics journal, Ed. Elsevier, Vol. 86, pp. 65-76, DOI: 10.1016/j.mejo.2019.02.019, avril 2019
 
 9 Kooli M., Di Natale G., Bosio A., Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. , DOI: 10.1007/s10836-019-05785-0, mars 2019
 
10 Vatajelu I., Di Natale G., High-Entropy STT-MTJ-based TRNG, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2018.2879439, février 2019
 
11 Plassan G., Morin-Allory K., Borrione D., Mining Missing Assumptions from Counter-Examples, Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 18, No. 1, DOI: 10.1145/3288759, janvier 2019
 
12 Martin H., Peris-Lopez P., Di Natale G., Taouil M., Hamdioui S., Enhancing PUF Based Challenge-Response Sets by Exploiting Various Background Noise Configurations, MDPI Electronics, Ed. MDPI, Vol. 8, No. 2, DOI: 10.3390/electronics8020145, janvier 2019
 
13 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk (Early Access), IEEE Transactions on Device and Materials Reliability, Vol. , DOI: 10.1109/TDMR.2018.2886463, décembre 2018
 
14 Anghel L., Benabdenbi M., Bosio A., Traiola M., Vatajelu I., Test and Reliability in Approximate Computing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 4, pp. 375-387, DOI: 10.1007/s10836-018-5734-9, août 2018
 
15 Leveugle R., Mkhinini A., Maistri P., Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption, Information - Open Access Journal of Information Science, Ed. MDPI, Vol. 9, No. 5, pp. 114, DOI: 10.3390/info9050114, mai 2018
 
16 Mkhinini A., Maistri P., Leveugle R., Tourki R., Co-designed accelerator for homomorphic encryption applications, Advances in Science, Technology and Engineering Systems Journal (ASTESJ), Vol. 3, No. 1, pp. 426-433, DOI: 10.25046/aj030152, février 2018
 
17 Vatajelu I., Prinetto P., Taouil M., Hamdioui S., Challenges and Solutions in Emerging Memory Testing, IEEE Transactions on Emerging Topics in Computing, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TETC.2017.2691263, 2017
 
18 Vatajelu I., Pouyan P., Hamdioui S., State of the art and challenges for test and reliability of emerging nonvolatile resistive memories, International Journal of Circuit Theory and Applications, Ed. Wiley, Chichester, UK, Vol. 46, No. 1, pp. 4-28, DOI: 10.1002/cta.2418, octobre 2017
 
19 Alexandrescu D., Altun M., Anghel L., Ciriani V., Tahoori M., Bernasconi A., Logic synthesis and testing techniques for switching nano-crossbar arrays, Microprocessors and Microsystems, Ed. Elsevier, Vol. 54, pp. 14-25, DOI: 10.1016/j.micpro.2017.08.004, octobre 2017
 
20 Javaheri N., Morin-Allory K., Borrione D., Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 869-882, DOI: 10.1109/TCAD.2016.2600241 , mai 2017
 
21 Deng E., Prenat G., Anghel L., Non-Volatile Magnetic Decider Based on Magnetic Tunnel Junctions, Electronics Letters, Ed. IEEE, Vol. , 2016
 
22 Pontié S., Maistri P., Leveugle R., Dummy operations in scalar multiplication over elliptic curves: a tradeoff between security and performance, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 23-36, DOI: 10.1016/j.micpro.2016.02.016, novembre 2016
 
23 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault models versus layout locality characteristics, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 64-73, DOI: 10.1016/j.micpro.2016.01.018, novembre 2016
 
24 Pierre L., Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 21, No. 2, pp. Article n°20, DOI: 10.1145/2811260, janvier 2016
 
25 Morin-Allory K., Javaheri N., Borrione D., Efficient and Correct by Construction Assertion-Based Synthesis, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 23, No. 12, pp. 2890-290, DOI: 10.1109/TVLSI.2014.2386212, décembre 2015
 
26 Ottavi M., Pontarelli S., Gizopoulos D., Bolchini C., Michael M.K., Anghel L., Tahoori M., Paschalis A., Reviriego P., Bringmann O., Izosimov V., Manhaeve H., Strydis C., Hamdioui S., Dependable Multicore Architectures at Nanoscale: The View From Europe , IEEE Design & Test, Ed. IEEE, Vol. 32, No. 2, pp. 17-28, DOI: 10.1109/MDAT.2014.2359572, avril 2015
 
27 O'Connor I., Liu J., Gaffiot F., Pregaldiny F., Maneux C., Lallement C., Goguet J., Fregonese S., Zimmer T., Anghel L., Leveugle R., Dang T., CNTFET modeling and reconfigurable logic circuit design, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 54, No. 11, pp. 2365-2379, DOI: 10.1109/TCSI.2007.907835 , novembre 2007
 
remonter

1 Brevets

1 Portolan M., Test apparatus and method for testing an integrated circuit, No. 17/54491, 19 mai 2017
 
remonter

24 Conférences invitées

 1 Regazzoni F., Bhasin S., Ali Pour A., Alshaer I., Aydin F., Aysu A., Beroulle V., Di Natale G., Franzon P., Hély D., Homma N., Ito A., Jap D., Kashyap P., Polian I., Potluri S., Ueno R., Vatajelu I., Yli-Mäyry V., Machine Learning and Hardware security: Challenges and Opportunities, Invited talk (Special Session), International Conference on Computer-Aided Design (ICCAD 2020), San Diego, UNITED STATES, 2 au 5 novembre 2020
 
 2 Vatajelu I., Reliability of neuromorphic computing, Invited Talk, GDR BioComp & SoC2: Quantum and Neuromorphic Technologies Meet, Palaiseau, FRANCE, 27 novembre 2019
 
 3 Anghel L., Managing Aging Induced Reliability at Run-time, Invited Talk, 7th Workshop on Cross-layer Resiliency (IWCR'2019), Stuttgart, GERMANY, 29 au 31 juillet 2019
 
 4 Vatajelu I., Randomness in emerging technologies: Functional robustness vs. security, Keynote in the Plenary Session, 7th Prague Embedded Systems Workshop (PESW'2019), Prague, CZECH REPUBLIC, 27 au 29 juin 2019
 
 5 Anghel L., Embedded Hardware Architectures for AI, Invited Talk, From Brain and Cognition to Artificial Intelligence Workshop, Grenoble, FRANCE, 4 juin 2019
 
 6 Vatajelu I., Fiabilité des architectures neuromorphiques, Invited Talk, GDR SoC2 Journée Thématique: Sécurité, fiabilité et test des SoC 2 : challenges et opportunités dans l’ère de l’IA, Paris, FRANCE, 16 mai 2019
 
 7 Maistri P., Secure Test Architectures in IoT, Invited Talk, European Nanoelectronics Applications, Design & Technology Conference (ADTC 2019), Dresden, GERMANY, 14 au 16 mai 2019
 
 8 Vatajelu I., Fault Modeling of Spiking Neural Networks with STDP, Plenary talk, BioComp 2019, Lille, FRANCE, 13 au 15 mai 2019
 
 9 Anghel L., Run-time Age Induced Reliability Prediction for SOC, Invited Talk, IEEE Latin America Test Symposium (LATS 2019), Santiago de Chile, CHILI, 11 au 13 mars 2019
 
10 Anghel L., Neuromorphic Circuits, Séminaire invité, L’Intelligence Naturelle au cœur des enjeux de l’Intelligence Artificielle – Les atouts du site grenoblois, Grenoble, FRANCE, 13 juillet 2018
 
11 Di Natale G., Kooli M., Bosio A., Portolan M., Leveugle R., Reliability of computing systems: from flip flops to variables, Invited talk (Special Session), 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, DOI: 10.1109/IOLTS.2017.8046242, 3 au 5 juillet 2017
 
12 Anghel L., Benabdenbi M., Bosio A., Vatajelu I., Test and reliability in approximate computing, Invited paper, Mixed Signals Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995210, 3 au 5 juillet 2017
 
13 Leveugle R., New approaches towards early dependability evaluation of digital integrated systems, Invited Tutorial, 11th IEEE International Design & Test Symposium (IDT'16), Hammamet, TUNISIA, 18 au 20 décembre 2016
 
14 Maistri P., Countermeasures against Implementation Attacks on Private- and Public-Key Cryptosystems, Keynote in the Opening Session, International Conference on Applications and Techniques in Information Security, Cairns, AUSTRALIA, 26 au 28 octobre 2016
 
15 Anghel L., Portolan M., Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue, Keynote talk, East West Design and test Symposium, Yerevan, ARMENIA, 13 au 16 octobre 2016
 
16 Leveugle R., DFT vs. Security - Is it a Contradiction? How Can We Get the Best of Both Worlds?, Invited Talk, 1st IEEE International Verification and Security Workshop, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
17 Pontié S., Prise en compte des fuites d’informations par canaux auxiliaires dans une implémentation ECC, Invited Talk, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 27 juin 2016
 
18 Portolan M., System Level Coordination of Multiple-Standard DfT, Invited Talk, Test Standards Application Workshop (TESTA’16), Amsterdam, NETHERLANDS, 28 mai 2016
 
19 Anghel L., System Failure Prediction with On-Chip Monitors, Plenary talk, Colloque National 2016 de GDR SOC-SIP, Nantes, FRANCE, 7 au 8 mai 2016
 
20 Portolan M., Standards: Can they co-exist for System Level Test?, Invited Talk, VLSI Test Symposium, Las Vegas, NE, UNITED STATES, 25 au 27 avril 2016
 
21 Borrione D., Automatic Synthesis of Verification IP's from Assertions: Beyond Observers, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16), Košice, SLOVENIA, 20 au 22 avril 2016
 
22 Anghel L., Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Vilard de Lans, FRANCE, 4 au 7 janvier 2016
 
23 Borrione D., Morin-Allory K., Liu M., Oddos Y., Morin-Allory K., Javaheri N., Verification and Synthesis of Digital Systems from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Villards de Lans, FRANCE, 1 janvier 2016
 
24 Anghel L., Reliability Measurements with In Situ Aging Monitors in FDSOI Technology, Invited talk (Elevator talk), International Test Conference (ITC'15), Anaheim, UNITED STATES, 6 au 8 octobre 2015
 
remonter

84 Conférences internationales

 1 Garay Trindade M., Garibotti R.F., Ost L., Letiche M., Beaucour J., Possamai Bastos R., Assessment of Machine Learning Algorithms for Near-Sensor Computing Under Radiation Soft Errors, IEEE International conference on electronics, circuits & systems (ICECS 2020), Glasgow, SCOTLAND, UNITED KINGDOM, 23 au 25 novembre 2020
 
 2 Laisne M., Crouch A., Portolan M., Keim M., Von Staudt H.M, Abdalwahab M., Van Treuren B., Rearick J., Modeling Novel Non-JTAG IEEE 1687-Like Architectures, International Test Conference (ITC 2020), Washington DC, UNITED STATES, 3 au 5 novembre 2020
 
 3 Anghel L., Cantoro R., Foti D., Portolan M., Sartoni S., Sonza Reorda M., New Perspectives on Core In-field Path Delay Test, International Test Conference (ITC 2020), Washington DC, UNITED STATES, 3 au 5 novembre 2020
 
 4 Di Natale G., Regazzoni F., Albanese V., Lhermet F., Loisel Y., Sensaoui A., Pagliarini S., Latest Trends in Hardware Security and Privacy, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2020), Rome, ITALY, 19 au 21 octobre 2020
 
 5 Cinçon V., Vatajelu I., Anghel L., Galy P., From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology, EUROSOI-ULIS 2020, Caen, FRANCE, 1 au 30 septembre 2020
 
 6 Portolan M., Silveira Feitoza R., Takam Tchendjou G., Reynaud V., Senthamarai Kannan K., Barragan M., Simeu E., Maistri P., Anghel L., Leveugle R., Mir S., A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System, 2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Naples (Napoli), ITALY, DOI: 10.1109/IOLTS50870.2020.9159721, 13 au 15 juillet 2020
 
 7 Papavramidou P., Nicolaidis M., Girard P., An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM, IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), pp. 1-6, Napoli, ITALY, DOI: 10.1109/IOLTS50870.2020.9159731, 13 au 15 juillet 2020
 
 8 Portolan M., Reynaud V., Maistri P., Leveugle R., Dynamic Authentication-Based Secure Access to Test Infrastructure, European Test Symposium (ETS 2020), Tallin, ESTONIA, 25 mai au 1 juin 2020
 
 9 Portolan M., Rearick J., Keim M., Linking Chip, Board, and System Test via Standards, European Test Symposium (ETS 2020), Tallinn, ESTONIA, 25 mai au 1 juin 2020
 
10 Di Natale G., Keren O., Nonlinear Codes for Control Flow Checking, IEEE European Test Symposium (ETS 2020), pp. 1-6, Tallinn, ESTONIA, DOI: 10.1109/ETS48528.2020.9131592, 25 au 29 mai 2020
 
11 Ali Pour A., Beroulle V., Cambou B., Danger J.-L., Di Natale G., Hély D., Guilley S., Karimi N., PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community, IEEE European Test Symposium (ETS 2020), Tallinn, ESTONIA, 25 mai au 1 juin 2020
 
12 Damljanovic A., Jutman A., Portolan M., Sanchez E., Squillero G., Tsertov A., Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL, International Test Conference (ITC 2019), Washington DC, UNITED STATES, 11 au 14 novembre 2019
 
13 Shah A., Cacho F., Anghel L., Aging Investigation of Digital Circuits using In-Situ Monitors, IEEE International Integrated Reliability Workshop (IIRW 2019), Stanford Sierra, Fallen Leaf Lake, UNITED STATES, 13 au 17 octobre 2019
 
14 Bosio A., Hamdioui S., O'Connor I., Rodrigues G., Lima F., Vatajelu I., Di Natale G., Anghel L., Nagarajan S., Fieback M.R., Rebooting Computing: The Challenges for Test and Reliability, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'2019), pp. 8138-8143, Noordwijk, NETHERLANDS, DOI: 10.1109/DFT.2019.8875270 , 2 au 4 octobre 2019
 
15 Galy P., De Conti L., Vinet M., Cristoloveanu S., Delahaye G., Anghel L., Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology, 30th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2019), Toulouse, FRANCE, 23 au 26 septembre 2019
 
16 Merandat M., Reynaud V., Valea E., Quévremont J., Maistri P., Leveugle R., Flottes M.-L., Dupuis S., Rouzeyre B., Di Natale G., A Comprehensive Approach to a Trusted Test Infrastructure, 4th International Verification and Security Workshop (IVSW 2019), Rhodes Island, GREECE, 1 au 3 juillet 2019
 
17 Bolchini C., Cassano L., Montalbano I., Reppole G., Zanetti A., Di Natale G., HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems, IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS'2019), Rhodes Island, GREECE, 1 au 3 juillet 2019
 
18 Vatajelu I., Di Natale G., Keren O., Martin H., On the Reliability of the Ring Oscillator Physically Unclonable Functions, IEEE 4th International Verification and Security Workshop (IVSW'2019), pp. 25-30, Rhodes Island, GREECE, DOI: 10.1109/IVSW.2019.8854401, 1 au 3 juillet 2019
 
19 Ait Said N., Benabdenbi M., Teaching Hardware/Software co-design using Rocket Chip, RISC V Workshop 2019, Zurich, SWITZERLAND, 11 au 13 juin 2019
 
20 Portolan M., Savino A., Leveugle R., Di Carlo S., Bosio A., Di Natale G., Alternatives to fault injections for early safety/security evaluations, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
21 Savino A., Portolan M., Leveugle R., Di Carlo S., Approximate computing design exploration through data lifetime metrics, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
22 Mosanu S., Guo X., Anghel L., Stan M., Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints, IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'2019), San Diego, UNITED STATES, 28 avril au 1 mai 2019
 
23 Valea E., Da Silva M., Flottes M.-L., Di Natale G., Rouzeyre B., Encryption-Based Secure JTAG, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), Cluj Napoca, ROMANIA, 24 au 26 avril 2019
 
24 Vatajelu I., Di Natale G., Anghel L., Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN), IEEE VLSI Test Symposium (VTS 2019), Monterey, UNITED STATES, 23 au 25 avril 2019
 
25 Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., On-Line Adjustable Precision Computing, Design & Technologies of Integrated Systems (DTIS 2019), Mykonos, GREECE, 16 au 18 avril 2019
 
26 Valea E., Da Silva M., Flottes M.-L., Di Natale G., Rouzeyre B., Dupuis S., Providing Confidentiality and Integrity in Ultra Low Power IoT Devices, 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS 2019), Mykonos, GREECE, DOI: 10.1109/DTIS.2018.8368561, 16 au 18 avril 2019
 
27 Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., Adjustable Precision Computing Using Redundant Arithmetic, Workshop on Approximate Computing (AxC'2019), Florence, ITALY, 29 mars 2019
 
28 Savino A., Portolan M., Di Carlo S., Leveugle R., Targeting approximation through data lifetime: a quest for optimization metrics, 4th Approximate Computing Workshop (AxC 2019), Florence, ITALY, 29 mars 2019
 
29 Di Natale G., Vatajelu I., Senthamarai Kannan K., Anghel L., Hidden-Delay-Fault Sensor for Test, Reliability and Security, IEEE Design Automation and Test Conference in Europe (DATE 2019), Florence, ITALY, 25 au 29 mars 2019
 
30 Ait Said N., Benabdenbi M., Villanova Novaes Magalhaes G., Mieux comprendre le lien matériel-logiciel en utilisant l’architecture RISC-V et la plateforme Rocket Chip, 15èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro-électronique et en nanotechnologies (JP-CNFM 2018), Saint-Malo, FRANCE, 7 au 9 novembre 2018
 
31 Anghel L., Di Natale G., Miramond B., Vatajelu I., Vianello E., Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies, 26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Verona, ITALY, 8 au 10 octobre 2018
 
32 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model, Fourteenth Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'2018), Amsterdam, NETHERLANDS, 13 septembre 2018
 
33 Morgül Muhammed Ceylan, Frontini L., Vatajelu I., Anghel L., Integrated Synthesis Methodology for Crossbar Arrays, IEEE NANOARCH'2018, Athens, GREECE, 18 au 19 juillet 2018
 
34 Vatajelu I., Anghel L., Portal J.-M., Bocquet M., Prenat G., Resistive and Spintronic RAMs: Device, Simulation, and Applications, IEEE International On Line Testing (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
35 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
36 Sivadasan A., Shah R., Cacho F., Anghel L., NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI, Design Automation and Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
37 Shah R., Cacho F., Anghel L., Investigation of speed sensors accuracy for process and aging compensation, IEEE International reliability Physics Symposium (IRPS'2018), San Francisco, UNITED STATES, 11 au 15 mars 2018
 
38 Plassan G., Morin-Allory K., Borrione D., Extraction of missing formal assumptions in under-constrained designs, 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), pp. 94-103, Vienna, AUSTRIA, DOI: 10.1145/3127041.3127046, 29 septembre au 2 octobre 2017
 
39 Pierre L., Chabot M., Assertion-Based Verification for SoC Models and Identification of Key Events, Euromicro Conference on Digital System Design (DSD 2017), Vienna, AUSTRIA, 30 août au 1 septembre 2017
 
40 Vatajelu I., Anghel L., Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2017), Newport, RI, UNITED STATES, DOI: 10.1109/NANOARCH.2017.8053727, 25 au 26 juillet 2017
 
41 Cacho F., Benhassain A., Shah R., Huard V., Anghel L., Investigation of critical path selection for in-situ monitors insertion, 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), pp. 247-252, Thessaloniki, GREECE, 3 au 5 juillet 2017
 
42 Vatajelu I., Di Natale G., Prinetto P., Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories, 2017 IEEE 2nd International Verification and Security Workshop (IVSW 2017), pp. 128-133, Thessaloniki, GREECE, DOI: 10.1109/IVSW.2017.8031552, 3 au 7 juillet 2017
 
43 Vatajelu I., Anghel L., Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing, International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, 3 au 5 juin 2017
 
44 Vatajelu I., Rodriguez-Montanes R., Renovell M., Figueras J., Mitigating Read & Write Errors in STT-MRAM Memories under DVS, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
45 Portolan M., Barragan M., Alhakim R., Mir S., Mixed-Signal BIST computation offloading using IEEE 1687, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
46 Mkhinini A., Maistri P., Leveugle R., Tourki R., HLS Design of a Hardware Accelerator for Homomorphic Encryption, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, GERMANY, DOI: 10.1109/DDECS.2017.7934578, 19 au 21 avril 2017
 
47 Barbareschi M., Bosio A., Hamdioui S., Nguyen Hoang Anh Du, Traiola M., Vatajelu I., Memristive devices: Technology, Design Automation and Computing Frontiers, International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), Palma de Mallorca, SPAIN, 4 au 6 avril 2017
 
48 Sivadasan A., Mhira S., Notin A., Benhassain A., Huard V., Maurin E., Cacho F., Anghel L., Bravaix A. , Architecture and Workload Dependant Digital Failure Rate, IEEE International Reliability for Physics of Semiconductors (IRPS 2017), Monterey, UNITED STATES, DOI: 10.1109/IRPS.2017.7936357, 2 au 6 avril 2017
 
49 Sivadasan A., Huard V., Anghel L., Worload Dependent Reliability Timing Analysis Flow, DATE 2017, Lausanne, SWITZERLAND, 27 au 29 mars 2017
 
50 Mkhinini A., Maistri P., Leveugle R., Tourki R., Machhout M., A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption, 11th IEEE International Design & Test Symposium (IDT'16), pp. 131-136, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
51 Terras L., Teglia Y., Agoyan M., Leveugle R., Taking into account indirect jumps or calls in continuous Control-Flow Checking, 11th IEEE International Design & Test Symposium (IDT'16), pp. 125-130, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
52 Portolan M., Accessing 1687 systems using arbitrary protocols, International Test Conference (ITC'16), Fort Worth, UNITED STATES, DOI: 10.1109/TEST.2016.7805839, 15 au 17 novembre 2016
 
53 Chabot M., Pierre L., Nabais-Moreno A., A Requirement Driven Testing Method for Multi-disciplinary System Design, ACM/IEEE International Conference on Model Driven Engineering Languages and Systems (MODELS'2016), Saint-Malo, FRANCE, 2 au 23 octobre 2016
 
54 Plassan G., Peter H.J., Morin-Allory K., Rahim F., Sarwary S., Borrione D., Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , pp. 1-6, Tallinn, ESTONIA, 26 au 28 septembre 2016
 
55 Chibani K., Portolan M., Leveugle R., Application-aware soft error sensitivity evaluation without fault injections - Application to Leon3, European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
56 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
57 Alexandrescu D., Altun M., Anghel L., Bernasconi A., Ciriani V., Frontini L., Tahoori M., Synthesis and Performance Optimization of a Switching Nano-crossbar Computer, Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Limassol, CYPRUS, 31 août au 2 septembre 2016
 
58 Deng E., Prenat G., Anghel L., Zhao W., Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions, 12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Beijing, CHINA, 18 au 20 juillet 2016
 
59 Chibani K., Portolan M., Leveugle R., Evaluating Application-Aware Soft Error Effects in Digital Circuits Without Fault Injections or Probabilistic Computations, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'16), pp. 54-59, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
60 Benhassain A., Mhira S., Cacho F., Huard V., Anghel L., In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability, International Verification and Security Workshop, Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
61 Leveugle R., Chahed A., Maistri P., Papadimitriou A., Hély D., Beroulle V., Ammari A., On Fault Injections for Early Security Evaluation vs. Laser-based Attacks, 1st IEEE International Verification and Security Workshop, pp. 33-38, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
62 Backenstrass T., Blot M., Pontié S., Leveugle R., Protection of ECC Computations against Side-Channel Attacks for Lightweight Implementations, 1st IEEE International Verification and Security Workshop, pp. 2-7, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
63 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
64 Thole N., Anghel L., Fey G., A Hybrid Algorithm to Conservatively Check the Robustness of Circuits, IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 26 mai 2016
 
65 Portolan M., A Novel Test Generation and Application Flow for Functional Access to IEEE 1687 instruments, IEEE European Test Symposium (ETS'2016), Amsterdam, NETHERLANDS, DOI: 10.1109/ETS.2016.7519302, 23 au 27 mai 2016
 
66 Portolan M., Rolland R., Student-driven development of a digital tester, European Workshop on Microelectronics Education (EWME'16), pp. 1-3, Southampton, ENGLAND, UNITED KINGDOM, DOI: 10.1109/EWME.2016.7496479, 11 mai 2016
 
67 Anghel L., Benhassain A., Sivadasan A., Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results, IEEE 34th VLSI Test Symposium (VTS'16), Las Vegas, NE, UNITED STATES, DOI: 10.1109/VTS.2016.7477316, 25 au 27 avril 2016
 
68 Benhassain A., Cacho F., Huard V., Mhira S., Anghel L., Parthasarathy C., Jain A., Sivadasan A., Robustness of Timing in-situ Monitors for AVS Management, IEEE International Reliability Physics Semiconductor (IRPS'16), Passadena, UNITED STATES, 17 au 21 avril 2017
 
69 Benhassain A., Cacho F., Huard V., Anghel L., Early failure prediction by using in-situ monitors: Implementation and application results, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
70 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
71 Ananiadis C., Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., On the development of a new countermeasure on a laser attack RTL fault model, Design, Automation and Test in Europe Conference (DATE'16), Dresden, GERMANY, 14 au 18 mars 2016
 
72 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Study of workload impact on BTI HCI induced aging of digital circuits, Design Automation and Test in Europe (DATE'16), Dresden, GERMANY, 14 au 17 mars 2016
 
73 Jayet-Griffon C., Cornelie M.-A., Maistri P., Elbaz-Vincent P., Leveugle R., Polynomial multipliers for Fully Homomorphic Encryption on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'15), Mayan Riviera, MEXICO, 7 au 9 décembre 2015
 
74 Benhassain A., Cacho F., Huard V., Saliva M., Anghel L., Parthasarathy C., Jain A., Giner F., Timing in-situ monitors: Implementation strategy and applications results, IEEE Custom Integrated Circuits Conference (ICICC'16), San Jose, CA, UNITED STATES, 28 au 30 septembre 2015
 
75 Chabot M., Mazet K., Pierre L., Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers, 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE’2015), Austin, Texas, UNITED STATES, 21 au 23 septembre 2015
 
76 Kebaili M., Morin-Allory K., Brignone J.C., Borrione D., Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
77 Javaheri N., Morin-Allory K., Borrione D., Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
78 Pierre L., Towards a Toolchain for Assertion-Driven Test Sequence Generation, Forum on specification & Design Languages (FDL’2015), Barcelona, SPAIN, 14 au 16 septembre 2015
 
79 Papadimitriou A., Tampas M., Hély D., Beroulle V., Maistri P., Leveugle R., Validation of RTL laser fault injection model with respect to layout information, IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), pp. 78-81, McLean, VA, UNITED STATES, 5 au 7 mai 2015
 
80 Rehman Saif-Ur, Benabdenbi M., Anghel L., Application-independent testing of multilevel interconnect in mesh-based FPGAs, IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), pp. 1-6, Naples, ITALY, DOI: 10.1109/DTIS.2015.7127383, 21 au 23 avril 2015
 
81 Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A. , Anghel L., Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology, IEEE International Reliability Physics Symposium (IRPS'15), pp. CA.4.1 - CA.4.6 , Monterrey, CA, UNITED STATES, DOI: 10.1109/IRPS.2015.7112782, 19 au 23 avril 2015
 
82 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault model versus layout locality characteristics, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
83 Pontié S., Maistri P., Leveugle R., Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
84 Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A. , Anghel L., Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI, Design, Automation & Test in Europe Conference & Exhibition (DATE'15), pp. 441-446, Grenoble, FRANCE, 9 au 13 mars 2015
 
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8 Chapitres de livre

1 Anghel L., Nicolaidis M., Design techniques to improve the resilience of computing systems: logic layer, Cross-Layer Reliability of Computing Systems, Giorgio DI NATALE, Dimitris GIZOPOULOS, Stefano DI CARLO, Alberto BOSIO, Ramon CANAL (Eds.) , Ed. IET - The Institution of Engineering and Technology, pp. 23-42, 2020
 
2 Bosio A., Di Carlo S., Di Natale G., Sonza Reorda M., Rodriguez Condia J.E., Design techniques to improve the resilience of computing systems: software layer, Cross-Layer Reliability of Computing Systems, Giorgio DI NATALE, Dimitris GIZOPOULOS, Stefano DI CARLO, Alberto BOSIO, Ramon CANAL (Eds.) , Ed. IET - The Institution of Engineering and Technology, pp. 95-112, 2020
 
3 Anghel L., Shah R., Cacho F., On-Chip Ageing Monitoring and System Adaptation, Ageing of Integrated Circuits: Causes, Effects and Mitigation TechniquesOn-Chip Ageing Monitoring and System Adaptation, B. Halak (Eds.) , Ed. , pp. 149-180, DOI: 10.1007/978-3-030-23781-3_6, 2019
 
4 Kiamehr S., Tahoori M., Anghel L., Manufacturing Threats, Dependable Multicore Architectures at Nanoscale, Marco Ottavi / Dimitris Gizopoulos / Salvatore Pontarelli (Eds.) , Ed. Springer , pp. 3-35, DOI: 10.1007/978-3-319-54422-9, 2017
 
5 Plassan G., Peter H.J., Morin-Allory K., Sarwary S., Borrione D., Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, revised selected contributions from 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Hollstein T., Raik J., Kostin S., Tšertov A., O'Connor I., Reis R (Eds.) , Ed. Springer , pp. 108-129, Vol. 508, DOI: 10.1007/978-3-319-67104-8, 2017
 
6 Benabdenbi M., Anghel L., Dimopoulos M., Gang Yi, Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip, Advances in Microelectronics: Reviews, Sergei Y. Yurish (Eds.) , Ed. IFSA, International Frequency Sensor Association, pp. 405-435, Vol. 1, 2017
 
7 Beroulle V., Candelier P., De Castro S., Di Natale G., Dutertre J.M., Flottes M.-L., Hély D., Hubert G., Leveugle R., Lu F., Maistri P., Papadimitriou A., Rouzeyre B., Tavernier C., Vanhauwaert P., Laser-induced fault effects in security-dedicated circuits, VLSI-SoC: Internet of Things Foundations, L. Claesen, M.-T. Sanz-Pascual, R. Reis, A. Sarmiento-Reyes (Eds.) , Ed. Elsevier, pp. 220-240, Vol. 464, 2015
 
8 Lazzari C., Anghel L., Reis R., A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming , VLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC’05) , Ed. Springer , pp. 331-344, Vol.240, DOI: DOI 10.1007/978-0-387-73661-7_21, 2007
 
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1 Livres & Éditions Ouvrages

1 Di Natale G., Gizopoulos D., Di Carlo S., Bosio A., Canal R. (Eds.) Cross-Layer Reliability of Computing Systems, pp. 1-328, Ed. IET - The Institution of Engineering and Technology, 2020
 
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2 Revues nationales

1 Ait Said N., Benabdenbi M., Villanova Novaes Magalhaes G., Prototypage Matériel-Logiciel de Systèmes Intégrés avec l'architecture RISC-V, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 18, No. Numéro spécial, janvier 2019
 
2 Fesquet L., Morin-Allory K., Rolland-Girod R., Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 14, No. 2009, pp. 9, DOI: 10.1051/j3ea/2015021 , août 2015
 
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3 Conférences nationales

1 Andrade Porras L.-L., Benabdenbi M., Muller O., Rousseau F., Pétrot F., Teaching basic computer architecture, assembly language programming, and operating system design using RISC-V, RISC V week 2019, Paris, FRANCE, 1 au 2 octobre 2019
 
2 Ait Said N., Benabdenbi M., LearnV: A Hardware/Software RISC V Based platform for Research and Education, Colloque National du GDR SoC2 2019, Montpellier, FRANCE, 19 au 21 juin 2019
 
3 Reynaud V., Maistri P., Leveugle R., Accès autorisé au réseau reconfigurable de test par ensemble de segments, 13ème Colloque du GDR SoC/SiP, Paris, FRANCE, 13 au 15 juin 2018
 
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14 Autres communications

 1 Maistri P., Dutertre J.M., Leveugle R., Laser Attacks against DDR Redundancy, Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices (SURREALIST'2018), Bremen, GERMANY, 2018
 
 2 Eggersglüß S., Hamdioui S., Jutman A., Michael M.K., Raik J., Sonza Reorda M., Tahoori M., Vatajelu I., IEEE European Test Symposium (ETS), IEEE International Test Conference (ITC'2019), Washington DC, UNITED STATES, DOI: 10.1109/ITC44170.2019.9000148, 2019
 
 3 Pontié S., Attaque par analyse de la puissance consommée contre un crypto-processeur basé sur les courbes Jacobi quartiques, Journées Codage et Cryptographie 2015, Toulon, FRANCE, 2015
 
 4 Portolan M., Cantoro R., Sanchez E., A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, European Test Symposium (ETS 2019), Baden Baden, GERMANY, 2019
 
 5 Elshamy M., Di Natale G., Pavlidis A., Louërat M.-M., Stratigopoulos H., Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism, IEEE European Test Symposium (ETS 2020), Tallinn, ESTONIA, 2020
 
 6 Pierre L., Runtime Verification of Embedded Systems Requirements throughout the Design Flow, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), Louvain-La-Neuve , BELGIUM, 2015
 
 7 Alipour A., Hély D., Beroulle V., Di Natale G., Power of Prediction: Advantages of Deep Learning Modeling as Replacement for Traditional PUF CRP Enrollment, TrueDevice Workshop 2020, Grenoble, FRANCE, 2020
 
 8 Roux J., Beroulle V., Morin-Allory K., Leveugle R., Bossuet L., Cezilly F., Berthoz F., Genevrier G., Cerisier F., Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems, 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2020), pp. 1-4, Novi Sad, SERBIE, DOI: 10.1109/DDECS50862.2020.9095559, 2020
 
 9 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
10 Vatajelu I., Di Natale G., High-Entropy STT-MTJ-based TRNG, 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'2019), Baden Baden, GERMANY, 2019
 
11 Portolan M., Cantoro R., Sanchez E., Sonza Reorda M., A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, International Test Conference (ITC 2018), Phoenix, UNITED STATES, 2018
 
12 Maistri P., Hardware Design of Error Detection Schemes for Symmetric Ciphers, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 2016
 
13 Anghel L., Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppb, Automotive Reliability and Test Workshop, Fort Worth, UNITED STATES, 2016
 
14 Valea E., Flottes M.-L., Di Natale G., Rouzeyre B., Stream Cipher Based Encryption in IEEE Test Standards, 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2019), Baden Baden, GERMANY, 2019
 
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5 Logiciels

1 Portolan M., "Manager for Soc Test" (MAST), Logiciel, 2 mai 2018
 
2 Leveugle R., Chibani K., Portolan M., EARS (Evaluation Avancée de Robustesse de Systèmes intégrés / Early Analysis of Robustness for integrated Systems), Logiciel, 30 décembre 2016
 
3 Leveugle R., AMfoRS' TIMA Emulation-based Fault Injection plaTform on Virtex-5, Plateforme, 26 juin 2015
 
4 Pierre L., Mazet K., Zian-Cherif A., OSIRIS version 1, Logiciel, 18 mars 2015
 
5 Ferro L., Pierre L., Chabot., Bel Hadj Amor Z., ISIS version 2.1.1, Logiciel, 1 mars 2015
 
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14 Thèses

 1 Shah R., Reliability Improvement by Dynamic Wearout Management using In-Situ Monitors, These de Doctorat, 5 octobre 2020
 
 2 Morin-Allory K., Assertions and hardware design, HDR, 15 novembre 2018
 
 3 Sivadasan A., Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability (confidential thesis - unavailable online), These de Doctorat, 29 juin 2018
 
 4 Plassan G., Conclusive formal verification of clock domain crossing properties, These de Doctorat, 28 mars 2018
 
 5 Mkhinini A., Hardware implementation of homomorphic encryption schemes, These de Doctorat, 14 décembre 2017
 
 6 Kebaili M., Reflections on the methodology for verifying multi-clock design : qualitative analysis and automation, These de Doctorat, 25 octobre 2017
 
 7 Benhassain A., Moniteurs de Vieillissement in-situ: Méthodologie d’intégration et application à la gestion dynamique de la fiabilité, These de Doctorat, 29 mai 2017
 
 8 Deng E., Design and development of low-power and reliable logic circuits based on spin-transfer torque magnetic tunnel junctions, These de Doctorat, 10 février 2017
 
 9 Pontié S., Hardware security for cryptography based on elliptic curves, These de Doctorat, 21 novembre 2016
 
10 Chibani K., Robustness analysis of digital integrated systems, These de Doctorat, 10 novembre 2016
 
11 Rehman Saif-Ur, Development of test and diagnosis techniques for hierarchical mesh-based FPGAs, These de Doctorat, 6 novembre 2015
 
12 Gang Yi, Design of a Network on chip (NoC) that tolerates multiple static and dynamic faults, These de Doctorat, 5 novembre 2015
 
13 Saliva M., Dedicated circuits to aging mechanisms study in avanced CMOS technology nodes: Design and measurements, These de Doctorat, 2 octobre 2015
 
14 Javaheri N., Automatic synthesis of digital circuits from temporal specifications, These de Doctorat, 1 octobre 2015
 
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