Publications

Publications

Recherche

Recherche

Auteur
hors TIMA
Équipe :

Mot clé
Type de publications
Tous
Sélectionne/déselectionne tous les types de publications
Journal art.
International National Tous
 Brevets  Conférences invitées
Conference art.
International National Tous
Chapitres de livre  Livres & Éditions Ouvrages
 Autres communications
 Logiciels  Thèses
 
 année
 

114 résultats

  15 Revues internationales
   1 Brevets
  14 Conférences invitées
  54 Conférences internationales
   3 Chapitres de livre
   1 Revues nationales
   1 Conférences nationales
   7 Autres communications
   5 Logiciels
  13 Thèses

15 Revues internationales

 1 Vatajelu I., Di Natale G., High-Entropy STT-MTJ-based TRNG, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2018.2879439, 2019
 
 2 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk (Early Access), IEEE Transactions on Device and Materials Reliability, Vol. , DOI: 10.1109/TDMR.2018.2886463, décembre 2018
 
 3 Anghel L., Benabdenbi M., Bosio A., Traiola M., Vatajelu I., Test and Reliability in Approximate Computing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 4, pp. 375-387, DOI: 10.1007/s10836-018-5734-9, août 2018
 
 4 Leveugle R., Mkhinini A., Maistri P., Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption, Information - Open Access Journal of Information Science, Ed. MDPI, Vol. 9, No. 5, pp. 114, DOI: 10.3390/info9050114, mai 2018
 
 5 Mkhinini A., Maistri P., Leveugle R., Tourki R., Co-designed accelerator for homomorphic encryption applications, Advances in Science, Technology and Engineering Systems Journal (ASTESJ), Vol. 3, No. 1, pp. 426-433, DOI: 10.25046/aj030152, février 2018
 
 6 Vatajelu I., Prinetto P., Taouil M., Hamdioui S., Challenges and Solutions in Emerging Memory Testing, IEEE Transactions on Emerging Topics in Computing, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TETC.2017.2691263, 2017
 
 7 Vatajelu I., Pouyan P., Hamdioui S., State of the art and challenges for test and reliability of emerging nonvolatile resistive memories, International Journal of Circuit Theory and Applications, Ed. Wiley, Chichester, UK, Vol. 46, No. 1, pp. 4-28, DOI: 10.1002/cta.2418, octobre 2017
 
 8 Alexandrescu D., Altun M., Anghel L., Ciriani V., Tahoori M., Bernasconi A., Logic synthesis and testing techniques for switching nano-crossbar arrays, Microprocessors and Microsystems, Ed. Elsevier, Vol. 54, pp. 14-25, DOI: 10.1016/j.micpro.2017.08.004, octobre 2017
 
 9 Javaheri N., Morin-Allory K., Borrione D., Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 869-882, DOI: 10.1109/TCAD.2016.2600241 , mai 2017
 
10 Deng E., Prenat G., Anghel L., Non-Volatile Magnetic Decider Based on Magnetic Tunnel Junctions, Electronics Letters, Ed. IEEE, Vol. , 2016
 
11 Pontié S., Maistri P., Leveugle R., Dummy operations in scalar multiplication over elliptic curves: a tradeoff between security and performance, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 23-36, DOI: 10.1016/j.micpro.2016.02.016, novembre 2016
 
12 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault models versus layout locality characteristics, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 64-73, DOI: 10.1016/j.micpro.2016.01.018, novembre 2016
 
13 Pierre L., Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 21, No. 2, pp. Article n°20, DOI: 10.1145/2811260, janvier 2016
 
14 Morin-Allory K., Javaheri N., Borrione D., Efficient and Correct by Construction Assertion-Based Synthesis, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 23, No. 12, pp. 2890-290, DOI: 10.1109/TVLSI.2014.2386212, décembre 2015
 
15 Ottavi M., Pontarelli S., Gizopoulos D., Bolchini C., Michael M.K., Anghel L., Tahoori M., Paschalis A., Reviriego P., Bringmann O., Izosimov V., Manhaeve H., Strydis C., Hamdioui S., Dependable Multicore Architectures at Nanoscale: The View From Europe , IEEE Design & Test, Ed. IEEE, Vol. 32, No. 2, pp. 17-28, DOI: 10.1109/MDAT.2014.2359572, avril 2015
 
remonter

1 Brevets

1 Portolan M., Test apparatus and method for testing an integrated circuit, No. 17/54491, 19 mai 2017
 
remonter

14 Conférences invitées

 1 Di Natale G., Kooli M., Bosio A., Portolan M., Leveugle R., Reliability of computing systems: from flip flops to variables, Invited talk (Special Session), 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, DOI: 10.1109/IOLTS.2017.8046242, 3 au 5 juillet 2017
 
 2 Anghel L., Benabdenbi M., Bosio A., Vatajelu I., Test and reliability in approximate computing, Invited paper, Mixed Signals Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995210, 3 au 5 juillet 2017
 
 3 Leveugle R., New approaches towards early dependability evaluation of digital integrated systems, Invited Tutorial, 11th IEEE International Design & Test Symposium (IDT'16), Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 4 Maistri P., Countermeasures against Implementation Attacks on Private- and Public-Key Cryptosystems, Keynote in the Opening Session, International Conference on Applications and Techniques in Information Security, Cairns, AUSTRALIA, 26 au 28 octobre 2016
 
 5 Anghel L., Portolan M., Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue, Keynote talk, East West Design and test Symposium, Yerevan, ARMENIA, 13 au 16 octobre 2016
 
 6 Leveugle R., DFT vs. Security - Is it a Contradiction? How Can We Get the Best of Both Worlds?, Invited Talk, 1st IEEE International Verification and Security Workshop, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 7 Pontié S., Prise en compte des fuites d’informations par canaux auxiliaires dans une implémentation ECC, Invited Talk, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 27 juin 2016
 
 8 Portolan M., System Level Coordination of Multiple-Standard DfT, Invited Talk, Test Standards Application Workshop (TESTA’16), Amsterdam, NETHERLANDS, 28 mai 2016
 
 9 Anghel L., System Failure Prediction with On-Chip Monitors, Plenary talk, Colloque National 2016 de GDR SOC-SIP, Nantes, FRANCE, 7 au 8 mai 2016
 
10 Portolan M., Standards: Can they co-exist for System Level Test?, Invited Talk, VLSI Test Symposium, Las Vegas, NE, UNITED STATES, 25 au 27 avril 2016
 
11 Borrione D., Automatic Synthesis of Verification IP's from Assertions: Beyond Observers, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16), Košice, SLOVENIA, 20 au 22 avril 2016
 
12 Anghel L., Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Vilard de Lans, FRANCE, 4 au 7 janvier 2016
 
13 Borrione D., Morin-Allory K., Liu M., Oddos Y., Morin-Allory K., Javaheri N., Verification and Synthesis of Digital Systems from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Villards de Lans, FRANCE, 1 janvier 2016
 
14 Anghel L., Reliability Measurements with In Situ Aging Monitors in FDSOI Technology, Invited talk (Elevator talk), International Test Conference (ITC'15), Anaheim, UNITED STATES, 6 au 8 octobre 2015
 
remonter

54 Conférences internationales

 1 Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., Adjustable Precision Computing Using Redundant Arithmetic, Workshop on Approximate Computing (AxC'2019), Florence, ITALY, 29 mars 2019
 
 2 Anghel L., Di Natale G., Miramond B., Vatajelu I., Vianello E., Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies, 26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Verona, ITALY, 8 au 10 octobre 2018
 
 3 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model, Fourteenth Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'2018), Amsterdam, NETHERLANDS, 13 septembre 2018
 
 4 Morgül Muhammed Ceylan, Frontini L., Vatajelu I., Anghel L., Integrated Synthesis Methodology for Crossbar Arrays, IEEE NANOARCH'2018, Athens, GREECE, 18 au 19 juillet 2018
 
 5 Vatajelu I., Anghel L., Portal J.-M., Bocquet M., Prenat G., Resistive and Spintronic RAMs: Device, Simulation, and Applications, IEEE International On Line Testing (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
 6 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
 7 Sivadasan A., Shah R., Cacho F., Anghel L., NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI, Design Automation and Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
 8 Shah R., Cacho F., Anghel L., Investigation of speed sensors accuracy for process and aging compensation, IEEE International reliability Physics Symposium (IRPS'2018), San Francisco, UNITED STATES, 11 au 15 mars 2018
 
 9 Plassan G., Morin-Allory K., Borrione D., Extraction of missing formal assumptions in under-constrained designs, 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), pp. 94-103, Vienna, AUSTRIA, DOI: 10.1145/3127041.3127046, 29 septembre au 2 octobre 2017
 
10 Pierre L., Chabot M., Assertion-Based Verification for SoC Models and Identification of Key Events, Euromicro Conference on Digital System Design (DSD 2017), Vienna, AUSTRIA, 30 août au 1 septembre 2017
 
11 Vatajelu I., Anghel L., Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2017), Newport, RI, UNITED STATES, 25 au 29 juillet 2017
 
12 Cacho F., Benhassain A., Shah R., Huard V., Anghel L., Investigation of critical path selection for in-situ monitors insertion, 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), pp. 247-252, Thessaloniki, GREECE, 3 au 5 juillet 2017
 
13 Vatajelu I., Di Natale G., Prinetto P., Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories, 2017 IEEE 2nd International Verification and Security Workshop (IVSW 2017), pp. 128-133, Thessaloniki, GREECE, DOI: 10.1109/IVSW.2017.8031552, 3 au 7 juillet 2017
 
14 Vatajelu I., Anghel L., Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing, International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, 3 au 5 juin 2017
 
15 Vatajelu I., Rodriguez-Montanes R., Renovell M., Figueras J., Mitigating Read & Write Errors in STT-MRAM Memories under DVS, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
16 Mkhinini A., Maistri P., Leveugle R., Tourki R., HLS Design of a Hardware Accelerator for Homomorphic Encryption, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, GERMANY, DOI: 10.1109/DDECS.2017.7934578, 19 au 21 avril 2017
 
17 Barbareschi M., Bosio A., Hamdioui S., Nguyen Hoang Anh Du, Traiola M., Vatajelu I., Memristive devices: Technology, Design Automation and Computing Frontiers, International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), Palma de Mallorca, SPAIN, 4 au 6 avril 2017
 
18 Sivadasan A., Benhassain A., Huard V., Cacho F., Anghel L., Architecture and Workload Dependant Digital Failure Rate, IEEE International Reliability for Physics of Semiconductors (IRPS 2017), Monterey, UNITED STATES, 2 au 6 avril 2017
 
19 Sivadasan A., Huard V., Anghel L., Worload Dependent Reliability Timing Analysis Flow, DATE 2017, Lausanne, SWITZERLAND, 27 au 29 mars 2017
 
20 Mkhinini A., Maistri P., Leveugle R., Tourki R., Machhout M., A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption, 11th IEEE International Design & Test Symposium (IDT'16), pp. 131-136, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
21 Terras L., Teglia Y., Agoyan M., Leveugle R., Taking into account indirect jumps or calls in continuous Control-Flow Checking, 11th IEEE International Design & Test Symposium (IDT'16), pp. 125-130, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
22 Portolan M., Accessing 1687 systems using arbitrary protocols, International Test Conference (ITC'16), Fort Worth, UNITED STATES, DOI: 10.1109/TEST.2016.7805839, 15 au 17 novembre 2016
 
23 Chabot M., Pierre L., Nabais-Moreno A., A Requirement Driven Testing Method for Multi-disciplinary System Design, ACM/IEEE International Conference on Model Driven Engineering Languages and Systems (MODELS'2016), Saint-Malo, FRANCE, 2 au 23 octobre 2016
 
24 Plassan G., Peter H.J., Morin-Allory K., Rahim F., Sarwary S., Borrione D., Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , pp. 1-6, Tallinn, ESTONIA, 26 au 28 septembre 2016
 
25 Chibani K., Portolan M., Leveugle R., Application-aware soft error sensitivity evaluation without fault injections - Application to Leon3, European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
26 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
27 Alexandrescu D., Altun M., Anghel L., Bernasconi A., Ciriani V., Frontini L., Tahoori M., Synthesis and Performance Optimization of a Switching Nano-crossbar Computer, Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Limassol, CYPRUS, 31 août au 2 septembre 2016
 
28 Deng E., Prenat G., Anghel L., Zhao W., Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions, 12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Beijing, CHINA, 18 au 20 juillet 2016
 
29 Chibani K., Portolan M., Leveugle R., Evaluating Application-Aware Soft Error Effects in Digital Circuits Without Fault Injections or Probabilistic Computations, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'16), pp. 54-59, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
30 Benhassain A., Mhira S., Cacho F., Huard V., Anghel L., In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability, International Verification and Security Workshop, Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
31 Leveugle R., Chahed A., Maistri P., Papadimitriou A., Hély D., Beroulle V., Ammari A., On Fault Injections for Early Security Evaluation vs. Laser-based Attacks, 1st IEEE International Verification and Security Workshop, pp. 33-38, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
32 Backenstrass T., Blot M., Pontié S., Leveugle R., Protection of ECC Computations against Side-Channel Attacks for Lightweight Implementations, 1st IEEE International Verification and Security Workshop, pp. 2-7, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
33 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
34 Thole N., Anghel L., Fey G., A Hybrid Algorithm to Conservatively Check the Robustness of Circuits, IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 26 mai 2016
 
35 Portolan M., A Novel Test Generation and Application Flow for Functional Access to IEEE 1687 instruments, IEEE European Test Symposium (ETS'2016), Amsterdam, NETHERLANDS, DOI: 10.1109/ETS.2016.7519302, 23 au 27 mai 2016
 
36 Portolan M., Rolland R., Student-driven development of a digital tester, European Workshop on Microelectronics Education (EWME'16), pp. 1-3, Southampton, ENGLAND, DOI: 10.1109/EWME.2016.7496479, 11 mai 2016
 
37 Anghel L., Benhassain A., Sivadasan A., Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results, IEEE 34th VLSI Test Symposium (VTS'16), Las Vegas, NE, UNITED STATES, DOI: 10.1109/VTS.2016.7477316, 25 au 27 avril 2016
 
38 Benhassain A., Cacho F., Huard V., Mhira S., Anghel L., Parthasarathy C., Jain A., Sivadasan A., Robustness of Timing in-situ Monitors for AVS Management, IEEE International Reliability Physics Semiconductor (IRPS'16), Passadena, UNITED STATES, 17 au 21 avril 2017
 
39 Benhassain A., Cacho F., Huard V., Anghel L., Early failure prediction by using in-situ monitors: Implementation and application results, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
40 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
41 Ananiadis C., Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., On the development of a new countermeasure on a laser attack RTL fault model, Design, Automation and Test in Europe Conference (DATE'16), Dresden, GERMANY, 14 au 18 mars 2016
 
42 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Study of workload impact on BTI HCI induced aging of digital circuits, Design Automation and Test in Europe (DATE'16), Dresden, GERMANY, 14 au 17 mars 2016
 
43 Jayet-Griffon C., Cornelie M.-A., Maistri P., Elbaz-Vincent P., Leveugle R., Polynomial multipliers for Fully Homomorphic Encryption on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'15), Mayan Riviera, MEXICO, 7 au 9 décembre 2015
 
44 Benhassain A., Cacho F., Huard V., Saliva M., Anghel L., Parthasarathy C., Jain A., Giner F., Timing in-situ monitors: Implementation strategy and applications results, IEEE Custom Integrated Circuits Conference (ICICC'16), San Jose, CA, UNITED STATES, 28 au 30 septembre 2015
 
45 Chabot M., Mazet K., Pierre L., Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers, 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE’2015), Austin, Texas, UNITED STATES, 21 au 23 septembre 2015
 
46 Kebaili M., Morin-Allory K., Brignone J.C., Borrione D., Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
47 Javaheri N., Morin-Allory K., Borrione D., Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
48 Pierre L., Towards a Toolchain for Assertion-Driven Test Sequence Generation, Forum on specification & Design Languages (FDL’2015), Barcelona, SPAIN, 14 au 16 septembre 2015
 
49 Papadimitriou A., Tampas M., Hély D., Beroulle V., Maistri P., Leveugle R., Validation of RTL laser fault injection model with respect to layout information, IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), pp. 78-81, McLean, VA, UNITED STATES, 5 au 7 mai 2015
 
50 Rehman Saif-Ur, Benabdenbi M., Anghel L., Application-independent testing of multilevel interconnect in mesh-based FPGAs, IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), pp. 1-6, Naples, ITALY, DOI: 10.1109/DTIS.2015.7127383, 21 au 23 avril 2015
 
51 Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A. , Anghel L., Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology, IEEE International Reliability Physics Symposium (IRPS'15), pp. CA.4.1 - CA.4.6 , Monterrey, CA, UNITED STATES, DOI: 10.1109/IRPS.2015.7112782, 19 au 23 avril 2015
 
52 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault model versus layout locality characteristics, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
53 Pontié S., Maistri P., Leveugle R., Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
54 Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A. , Anghel L., Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI, Design, Automation & Test in Europe Conference & Exhibition (DATE'15), pp. 441-446, Grenoble, FRANCE, 9 au 13 mars 2015
 
remonter

3 Chapitres de livre

1 Plassan G., Peter H.J., Morin-Allory K., Sarwary S., Borrione D., Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, revised selected contributions from 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Hollstein T., Raik J., Kostin S., Tšertov A., O'Connor I., Reis R (Eds.) , Ed. Springer , pp. 108-129, Vol. 508, DOI: 10.1007/978-3-319-67104-8, 2017
 
2 Benabdenbi M., Anghel L., Dimopoulos M., Gang Yi, Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip, Advances in Microelectronics: Reviews, Sergei Y. Yurish (Eds.) , Ed. IFSA, International Frequency Sensor Association, pp. 405-435, Vol. 1, 2017
 
3 Beroulle V., Candelier P., De Castro S., Di Natale G., Dutertre J.M., Flottes M.-L., Hély D., Hubert G., Leveugle R., Lu F., Maistri P., Papadimitriou A., Rouzeyre B., Tavernier C., Vanhauwaert P., Laser-induced fault effects in security-dedicated circuits, VLSI-SoC: Internet of Things Foundations, L. Claesen, M.-T. Sanz-Pascual, R. Reis, A. Sarmiento-Reyes (Eds.) , Ed. Elsevier, pp. 220-240, Vol. 464, 2015
 
remonter

1 Revues nationales

1 Fesquet L., Morin-Allory K., Robin R., Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 14, No. 2009, pp. 9, DOI: 10.1051/j3ea/2015021 , août 2015
 
remonter

1 Conférences nationales

1 Reynaud V., Maistri P., Leveugle R., Accès autorisé au réseau reconfigurable de test par ensemble de segments, 13ème Colloque du GDR SoC/SiP, Paris, FRANCE, 13 au 15 juin 2018
 
remonter

7 Autres communications

1 Maistri P., Dutertre J.M., Leveugle R., Laser Attacks against DDR Redundancy, Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices (SURREALIST'2018), Bremen, GERMANY, 2018
 
2 Pontié S., Attaque par analyse de la puissance consommée contre un crypto-processeur basé sur les courbes Jacobi quartiques, Journées Codage et Cryptographie 2015, Toulon, FRANCE, 2015
 
3 Pierre L., Runtime Verification of Embedded Systems Requirements throughout the Design Flow, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), Louvain-La-Neuve , BELGIUM, 2015
 
4 Portolan M., Barragan M., Alhakim R., Mir S., Mixed-Signal BIST computation offloading using IEEE 1687, European Test Symposium (ETS 2017), Limassol, CYPRUS, 2017
 
5 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
6 Maistri P., Hardware Design of Error Detection Schemes for Symmetric Ciphers, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 2016
 
7 Anghel L., Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppb, Automotive Reliability and Test Workshop, Fort Worth, UNITED STATES, 2016
 
remonter

5 Logiciels

1 Portolan M., "Manager for Soc Test" (MAST), Logiciel, 2 mai 2018
 
2 Leveugle R., Chibani K., Portolan M., EARS (Evaluation Avancée de Robustesse de Systèmes intégrés / Early Analysis of Robustness for integrated Systems), Logiciel, 30 décembre 2016
 
3 LEVEUGLE R., AMfoRS' TIMA Emulation-based Fault Injection plaTform on Virtex-5, Plateforme, 26 juin 2015
 
4 Pierre L., Mazet K., Zian-Cherif A., OSIRIS version 1, Logiciel, 18 mars 2015
 
5 Ferro L., Pierre L., Chabot., Bel Hadj Amor Z., ISIS version 2.1.1, Logiciel, 1 mars 2015
 
remonter

13 Thèses

 1 Morin-Allory K., Assertions and hardware design, HDR, 15 novembre 2018
 
 2 Sivadasan A., Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability (confidential thesis), These de Doctorat, 29 juin 2018
 
 3 Plassan G., Conclusive formal verification of clock domain crossing properties, These de Doctorat, 28 mars 2018
 
 4 Mkhinini A., Hardware implementation of homomorphic encryption schemes, These de Doctorat, 14 décembre 2017
 
 5 Kebaili M., Reflections on the methodology for verifying multi-clock design : qualitative analysis and automation, These de Doctorat, 25 octobre 2017
 
 6 Benhassain A., Moniteurs de Vieillissement in-situ: Méthodologie d’intégration et application à la gestion dynamique de la fiabilité, These de Doctorat, 29 mai 2017
 
 7 Deng E., Design and development of low-power and reliable logic circuits based on spin-transfer torque magnetic tunnel junctions, These de Doctorat, 10 février 2017
 
 8 Pontié S., Hardware security for cryptography based on elliptic curves, These de Doctorat, 21 novembre 2016
 
 9 Chibani K., Robustness analysis of digital integrated systems, These de Doctorat, 10 novembre 2016
 
10 Rehman Saif-Ur, Development of test and diagnosis techniques for hierarchical mesh-based FPGAs, These de Doctorat, 6 novembre 2015
 
11 Gang Yi, Design of a Network on chip (NoC) that tolerates multiple static and dynamic faults, These de Doctorat, 5 novembre 2015
 
12 Saliva M., Dedicated circuits to aging mechanisms study in avanced CMOS technology nodes: Design and measurements, These de Doctorat, 2 octobre 2015
 
13 Javaheri N., Automatic synthesis of digital circuits from temporal specifications, These de Doctorat, 1 octobre 2015
 
remonter