TIMA laboratory


Le prochain Conseil Scientifique aura lieu le

24/10/2019 - de 14 h 00 à 16 h 30, Laboratoire TIMA - Salle T312, FRANCE


12th International Conference on Advances in Circuits, Electronics and Micro-electronics

Venue: Nice, FRANCE
Date: October 27-31, 2019

industry/research committee : FESQUET L. technical program committee : FESQUET L.

37th IEEE International Conference on Computer Design

Date: November 17-20, 2019

technical program committee : VATAJELU E.I.

Summary: The IEEE International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies.

The 19th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications

Venue: Krakow, POLAND
Date: December 2-6, 2019

steering committee member : BASROUR S.

Summary: The PowerMEMS conference provides an excellent opportunity to bring together world scientists and engineers from academia, research institutes and companies to present and discuss the latest results in the general fields of miniaturized devices and systems for power generation and energy conversion in micro and nano scales. We warmly accept wide range of topics, from basic principles, materials and fabrication ending on applications and markets in all energy domains including, but not limited to: electrical, mechanical, chemical, thermal, magnetic, electrostatic, ferroelectric, optical, nuclear, and fluidic. The conference goals are to stimulate interaction and knowledge exchange between the delegates in a friendly atmosphere.

Asian Hardware Oriented Security and Trust Symposium

Venue: Xi'an, CHINA
Date: December 10-12, 2019

european projects chair : DI NATALE Giorgio

Summary: Asian Hardware Oriented Security and Trust Symposium (AsianHOST) is an annual symposium which aims to facilitate the rapid growth of hardware-based security research and development. Another goal of this conference is to help build hardware security community in Asian and Pacific area.

PhD thesis defenses

« Fault Tolerance and Reliability for Partially Connected 3D Networks-on-Chip ».

Candidate: A. Coelho

Advisor: R. Velazco

President of jury: L. Naviner

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Electronique, électrotechnique, automatique

Defense: October 25th, 2019 - 14:00, MINATEC - Amphi Z108


Networks-on-Chip (NoC) have emerged as a viable solution for the communication challenges in highly complex Systems-on-Chip (SoC). The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and Networks-on-Chip (NoC) schemes provide the possibility of designing a high-performance system in a limited chip area. The major advantages of Three-Dimensional Networks-on-Chip (3D-NoCs) are a considerable reduction in the average wire length and wire delay, resulting in lower power consumption and higher performance. However, 3D-NoCs suffer from some reliability issues such as the process variability of 3D-IC manufacturing. In particular, the low yield of vertical connection significantly impacts the design of three-dimensional die stacks with a large number of Through Silicon Via (TSV). Equally concerning, advances in integrated circuit manufacturing technologies are resulting in a potential increase in their sensitivity to the effects of radiation present in the environment in which they will operate. In fact, the increasing number of transient faults has become, in recent years, a major concern in the design of critical SoC. As a result, the evaluation of the sensitivity of circuits and applications to events caused by energetic particles present in the real environment is a major concern that needs to be addressed. So, this thesis presents contributions in two important areas of reliability research: in the design and implementation of deadlock-free fault-tolerant routing schemes for the emerging three-dimensional Networks-on-Chips; and in the design of fault injection frameworks able to emulate single and multiple transient faults in the HDL-based circuits. The first part of this thesis addresses the issues of transient and permanent faults in the architecture of 3D-NoCs and introduces a new resilient routing computation unit as well as a new runtime fault-tolerant routing scheme. A novel resilient mechanism is introduced in order to tolerate transient faults occurring in the route computation unit (RCU), which is the most important logical element in NoC routers. Failures in the RCU can provoke misrouting, which may lead to severe effects such as deadlocks or packet loss, corrupting the operation of the entire chip. By combining a reliable fault detection circuit leveraging circuit-level double-sampling, with a cost-effective rerouting mechanism, we develop a full fault-tolerance solution that can efficiently detect and correct such fatal errors before the affected packets leave the router. Yet in the first part of this thesis, a novel fault-tolerant routing scheme for vertically-partially-connected 3D Networks-on-Chip called FL-RuNS is presented. Thanks to an asymmetric distribution of virtual channels, FL-RuNS can guarantee 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. With the aim to emulate the radiation effects on new SoCs designs, the second part of this thesis addresses the fault injection methodologies by introducing two frameworks named NETFI-2 (Netlist Fault Injection) and NoCFI (Networks-on-Chip Fault Injection). NETFI-2 is a fault injection methodology able to emulate transient faults such as Single Event Upsets (SEU) and Single Event Transient (SET) in a HDL-based (Hardware Description Language) design. Extensive experiments performed on two appealing case studies are presented to demonstrate NETFI-2 features and advantage. Finally, in the last part of this work, we present NoCFI as a novel methodology to inject multiple faults such as MBUs and SEMT in a Networks-on-Chip architecture. NoCFI combines ASIC-design-flow, in order to extract layout information, and FPGA-design-flow to emulate multiple transient faults.



Winner of PhD Forum at VLSI-SoC'2019

Award: Winner of PhD Forum at VLSI-SoC'2019 (27th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 6-9, 2019
Place: Cuzco (PERU)
Title: A Digital Event-Based Strategy for ASK demodulation
- Rodrigo IGA JADUE (TIMA - CDSI team)
- Sylvain ENGELS (TIMA - CDSI team)
- Laurent FESQUET (TIMA - CDSI team)


Best Paper Award at DDECS'2019 (Cluj Napoca, ROMANIA)

Award: Best Paper Award at DDECS'2019 (22nd International Symposium on Design and Diagnostics of Electronics Circuits and Systems)
Date : April 24-26, 2019
Place : Cluj Napoca (ROMANIA)
Title : "Encryption-Based Secure JTAG"
Authors :
- Emanuele VALEA (LIRMM, Montpellier)
- Mathieu DA SILVA (LIRMM, Montpellier)
- Marie-Lise FLOTTES (LIRMM, Montpellier)
- Giorgio DI NATALE (TIMA, AMfoRS team, Grenoble)
- Bruno ROUZEYRE (LIRMM, Montpellier)


IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Award: The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

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Post-doc : Calcul embarqué pour l’imagerie hyper-spectrale

Host: TIMA Laboratory - CDSI team - 46 avenue Félix Viallet - 38031 GRENOBLE Cedex

Start Date: February 1st, 2020

Duration: 24 months

Profile: Le projet collaboratif ImSpoc-UV porté par la société Pyxalis a pour objectif la conception d’une caméra hyperspectrale dans le proche Ultra Violet à partir du capteur d’image très haute performance HDPyx et d’un système optique sur la puce spécifique. Ce système optique produit des interférogrammes acquis par le capteur en une seule prise, puis le spectre est obtenu par un calcul approprié à partir dEn collaboration avec les spécialistes du traitement de l’image, vous contribuerez à l’élaboration d’algorithmes efficaces et parallélisable. Accompagné par des experts en électronique, vous serez en charge de la partie numérique à intégrer sur des plateformes conçues par ailleurs. e ces données.

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Contact person: Stéphane MANCINI



Post-doc position in digital hardware for AI

Host: TIMA Laboratory - SLS team - 46 avenue Félix Viallet - 38031 GRENOBLE Cedex

Start Date: September 2019

Duration: 1 year, possibly renewable 1 once

Profile: See complete information to : follow the link

Contact person: Frédéric PETROT / Liliana ANDRADE



Research engineer position in digital hardware for AI

Host: TIMA Laboratory - SLS team - 46 avenue Félix Viallet - 38031 GRENOBLE Cedex

Start Date: September 2019

Duration: 1 year

Profile: See complete information to : follow the link

Contact person: Frédéric PETROT / Liliana ANDRADE