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Conferences

16th International School on the Effects of Radiation on Embedded Systems for Space Applications

SERESSA
Venue: Virtual event from Porto Alegre (Brazil), BRAZIL
Date: December 1-4, 2020

Summary: SERESSA combines academic, government, and industrial communities working in the area of radiation effects on embedded systems. Radiation effects are a significant concern for space and avionics systems, as well as for critical applications operating at ground level such as automotive, high energy facilities, medical or even banking. The school is based on lectures and exercises involving real case studies using the common tools of the domain. The intended audience includes both beginning and experienced researchers, engineers, and post-graduate students wishing to enhance their knowledge base in this rapidly evolving field. Topics covered by SERESSA include: radiation environment, spacecraft anomalies, single-event effects (SEE), total dose effects (TID), radiation effects in power systems, radiation effects in solar cells, architecture hardening in analog, and digital circuits and in memories, software hardening, effects in FPGAs, hardness assurance, rate prediction, radiation testing, laser testing and remote testing experiments. First SERESSA was organised in 2005, in the middle of the Amazon Jungle, Manaus, Brazil. Then, it moved around the world, being organised in Seville, Buenos Aires, Palm Beach, Takasaki, São José dos Campos, Toulouse, Ansan, Moscow, Bariloche, Puebla, Montreal, Munich, Nordwick and Seville. Now, in 2020, celebration of 15 years of SERESSA, it will be a fully Virtual Edition, from Porto Alegre, Brazil.

PhD thesis defenses

« Currently there is no defense planned »

Awards


Best reading paper - Transactions of Microwave Theory and Techniques (December 2020 issue)

Award: Best reading paper - Transactions of Microwave Theory and Techniques
Date: December 2020 issue
Title: Design of mm-Wave Slow-wave Coupled Coplanar Waveguides (TMTT-2020-04-0426)
Authors:
- Marc MARGALEF-ROVIRA, IEEE member (TIMA - RMS team)
- Jose LUGO-ALVAREZ (CEA LETI)
- Alfredo BAUTISTA (Advanced Silicon)
- Loic VINCENT (Grenoble INP)
- Sylvie LEPILLIET (IEMN)
- Abdelhalim A. SAADI (RFIC-Lab)
- Florence PODEVIN, IEEE member (RFIC-Lab)
- Manuel J. BARRAGAN, IEEE member (TIMA - RMS team)
- Emmanuel PISTONO (RFIC-Lab)
- Sylvain BOURDEL (RFIC-Lab)
- Christophe GAQUIERE (IEMN)
- Philippe FERRARI, IEEE Senior Member (RFIC-Lab)

 

Winner of PhD Forum at VLSI-SoC'2019 (Cuzco, PERU)

Award: Winner of PhD Forum at VLSI-SoC'2019 (27th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 6-9, 2019
Place: Cuzco (PERU)
Title: A Digital Event-Based Strategy for ASK demodulation
Authors:
- Rodrigo IGA JADUE (TIMA - CDSI team)
- Sylvain ENGELS (TIMA - CDSI team)
- Laurent FESQUET (TIMA - CDSI team)

 

Best Paper Award at DDECS'2019 (Cluj Napoca, ROMANIA)

Award: Best Paper Award at DDECS'2019 (22nd International Symposium on Design and Diagnostics of Electronics Circuits and Systems)
Date : April 24-26, 2019
Place : Cluj Napoca (ROMANIA)
Title : "Encryption-Based Secure JTAG"
Authors :
- Emanuele VALEA (LIRMM, Montpellier)
- Mathieu DA SILVA (LIRMM, Montpellier)
- Marie-Lise FLOTTES (LIRMM, Montpellier)
- Giorgio DI NATALE (TIMA, AMfoRS team, Grenoble)
- Bruno ROUZEYRE (LIRMM, Montpellier)

 

Jobs

Post-doctoral/Research engineer position: Inference on the Edge for Semiconductor Packaging Classification

Host: SLS (System Level Synthesis)

Start Date: ASAP

Duration: 1 year

Profile: Context:
The context of the work is related to inference at the "Edge", targeting small, power efficient, yet accurate enough application specific artificial neural networks. Classical inference techniques makes use of large artificial neural networks, that require lots of memory and computing resources. However, many applications have to run on limited resources, typically embedded processors, either alone or linked to small amount of FPGA resources. This latter system architecture is what is targeted in this work.

Work to be done:
Scientific:
The work targets the definition and implementation of a system for "Edge" computing targeting the binary classification of integrated circuit packaging: a package is either accepted or rejected. The system is based on the ST-Microelectronics MP1A embedded board connected to the FPGA of a Zybo Z7 board through the Ethernet plug. It receives a real-time flow of images that have to be classified depending on a bunch of industry specific criteria (voids, cracks, shapes, colors, ...), for at the end, deciding upon rejection or acceptance of a given package. Given the throughput of the production line, the binary classification decision must be taken with low latency and high-throughput. It must also be done with low resource usage, in particular fit on a relatively small FPGA.
The SLS group at TIMA has been working on balanced ternary ({−1, 0, 1}) neural networks for image classification, and the target is to evaluate the usage of ternary neurons in the context of binary classification. The topic to be addressed are:
• choice of a ANN architecture for package fault detection: MLP, CNN, RCNN, ... The requires studying the state of the art and experimenting on the data provided by STMicro
• definition/adaption of a learning algorithm for this specific application
• porting to learning algorithm on highly quantized weights and activation. Experimentations can be done with different constrains (balanced binary, balanced ternary, ...), to evaluate the performance/accuracy trade-offs
• support for the implementation of the ANN and the demonstration on the whole system

Other:
Application of the research will be done within the framework of the EU funded Artificial Intelligence for Digitizing Industry (AI4DI) project in close cooperation with ST-Microelectronics and CEA-LIST in France. This means contributing to the writing of project deliverables, reporting on the work done regularly, participating to (currently virtual) meetings in Europe at large, and cooperating in particular with the French partners. Although the subject is clearly application oriented, the candidate is expected to propose innovative solutions, and produce new ideas and results suitable for publication in scientific journals and conferences. This is also a tangible outcome that is expected within the AI4DI project.

Prerequisite:
The candidate is expected to have a PhD (post-doc) or Engineering degree (research engineer) in computer science or computer engineering. It must demonstrate a strong background in either hardware/software codesign and FPGA implementation, or in artificial intelligence and neural network, with an interest in practical implementation.
In any case, basic operational knowledge in usage of the deep-learning framework (pytorch, tensor- flow, keras, ...) is needed, and interest in compilation frameworks like glow, xla, N2D2, ..., is a plus.

Salary:
Funding is granted through the AI4DI European project. Salary depends on experience.

See complete information

Contact person: Frédéric PETROT: frederic??petrot(at)univ-grenoble-alpes??fr

 

 

Post-doctoral position: Quantized Neural Networks for High-Efficiency Inference

Host: SLS (System Level Synthesis)

Start Date: ASAP

Duration: 1 year

Profile: Context:
The overall context of the work is related to hardware acceleration of inference, targeting power efficient, application specific artificial neural networks. Classical inference techniques makes use of large artificial neural networks, that require lots of memory and computing resources. However, many applications have either to run on limited resources, typically embedded processors, or minimize resource usage, such as large scale inference in servers. All major players in the cloud services are currently developing their own hardware accelerators for inference, and the size of the parameters and activations is critical for the performance/accuracy trade-off.

Research:
The System Level Synthesis group at TIMA has been working on the design of highly quantized (more specifically ternary) neural networks for image classification, targeting FPGA implementations. In such networks, all but the first layer manipulate only ternary {−1, 0, 1} values for both parameters and activations, which leads to very dense and low power hardware implementations. However, learning for highly quantized neural networks is a subject of research by itself, and we worked in cooperation with a team at the LIG lab to devise a first approach back in 2017. Already at that time, and since then, quite a few teams have put efforts on this topic, but we believe there is still room for improvement and generalization.
In this context, the purpose of the post-doc position is to study learning strategies for inference with a small number of bits (binary, ternary, or a bit more, balanced or not), or with values that can be easily computed in hardware (integral power of 2, ...), and possibly combined with deep compression approaches.
The target applications are typically image classification (binary or n-ary), image segmentation, but may also span other domains, such as sentence recognition for embedded devices or cloud-based recommendation systems. Although constrained to neural networks, a lot of freedom is given concerning strategies and approaches that can be used to perform this task, and the candidate is expected to use her/his expertise to search for innovative solutions to advance knowledge in this area.
Note that the SLS team at TIMA is specialized in designing innovative hardware accelerators, not in machine learning. However, the research takes place in the context of the state funded Multidisciplinary Institute in Artificial Intelligence (MIAI), enabling cooperation within a large ecosystem of recognized teams and individuals in the machine learning area.

Prerequisite:
The candidate is expected to have a PhD (post-doc) or Engineering degree (research engineer) in computer science or computer engineering. It must demonstrate a strong background in artificial intelligence and neural networks, with a interest in practical implementation. Operational knowledge in usage of a deep-learning framework (pytorch, tensorflow, keras, ...) is needed, and basic knowledge in compilation frameworks like glow, xla, N2D2, ..., is a plus. Finally, interest in hardware implementation is useful, to grasp the actual constraints of the implementation.

Team bibliography related to the subject:
Journals and conferences:
• Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot: Efficient Decompression of Binary Encoded Balanced Ternary Sequences. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1962-1966 (2019)
• Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot: High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression. ACM Trans. Reconfigurable Technol. Syst. 11(3): 15:1-15:24 (2018)
• Liliana Andrade, Adrien Prost-Boucle, Frédéric Pétrot: Overview of the state of the art in embedded machine learning. DATE 2018: 1033-1038
• Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy: Scalable high-performance architecture for convolutional ternary neural networks on FPGA. FPL 2017: 1-7
• Hande Alemdar, Vincent Leroy, Adrien Prost-Boucle, Frédéric Pétrot: Ternary neural networks for resource-efficient AI applications. IJCNN 2017: 2547-2554

Invited talks:
• Applied Machine Learning Days (AMLD-2020, Lausanne, CH): https://appliedmldays. org/tracks/ai-ml-on-the-edge
• International Workshop on Highly Efficient Neural Processing (HENP-2018, Torino, IT): http: //cmalab.snu.ac.kr/HENP2018

Salary:
Funding is granted through the MIAI institute in Grenoble, France. Salary depends on experience.

See complete information

Contact person: Frédéric PETROT: frederic??petrot(at)univ-grenoble-alpes??fr