TIMA laboratory


MIAI GRENOBLE ALPES - TIMA a obtenu deux chaires MIAI et encadrera des thèses


(Multidisciplinary Institute in Artificial Intelligence)

Chair title: Digital Hardware AI Architectures
Chair holder(s): Frédéric PETROT (TIMA - SLS team)
Financed by: ANR - PIA
In short:
According to a recent Facebook analysis, AI tasks need a 100x power reduction in the coming years to be sustainable. This chair focuses on highly energy efficient hardware/software architectures integration of AI and deep-learning to take up this challenge.
• Google France
• Kalray
• STMicroelectronics
• Upmem

Chair title: Hardware for spike-coded neural networks exploiting hybrid CMOS non-volatile technologies
Chair holder(s): Lorena ANGHEL (TIMA - AMfoRS team)
Financed by: ANR - PIA
In short:
Spiking Neural Networks are seen as a Key building block for strongly improving the energy efficiency of current AI applications and opening up new possibilities (in terms of unsupervised learning, recurrent networks, probabilistic inference, etc.). In that respect, the Grenoble R&D ecosystem has key strengths, especially its capability to design and manufacture embedded systems in advanced hybrid CMOS-Non Volatile Memory (NVM) technology. The scientific challenges to be tackled are the following. The first one is to define power-constrained learning and inference algorithms (online, supervised, unsupervised, probabilistic, etc.). The second one is to design a scalable and flexible SNN architecture, adaptable to the different above-mentioned algorithms, and fabricate that circuit in hybrid nanoscale CMOS and NVM technology, enabling very dense synaptic density. The last objective is to derive a principled toolchain for the algorithm, design, development, and integration of spiking neural networks for future adoption in industrial health and automotive embedded applications.

"TIMA Scientific Days - AMS-RF circuits and systems" will take place on

April 4th, 2020 - From 14:00 to 18:00, Grenoble INP - Amphi Gosse, FRANCE

These Scientific Days are meant to present the research topics and to disseminate the recent advances of TIMA researchers. These presentations are open to everybody, whether they are members of TIMA or not.

Manuel BARRAGAN (TIMA - RMS team)
Ioana VATAJELU (TIMA - AMfoRS team)
Invited talk: Guillaume PRENAT (Spintec)
Mohamed AKRARAI (TIMA - CDSI team)
Breytner J. FERNANDEZ MESA (TIMA - SLS team)

See complete information


38th IEEE VLSI Test Symposium

Venue: San Diego, USA
Date: April 5-8, 2020

general chair : ANGHEL L. publication chair : VATAJELU E.I. technical program committee : BARRAGAN M., DI NATALE Giorgio, MIR S.

23rd Symposium on Design & Diagnostics of Electronic Circuits & Systems

Venue: Novi Sad, SERBIA
Date: April 22-24, 2020

technical program committee : BARRAGAN M., LEVEUGLE R., MAISTRI P., PIERRE L., PORTOLAN M., VATAJELU E.I.

IEEE International Symposium on Circuits and Systems

Venue: Seville, SPAIN
Date: May 17-20, 2020

technical program committee : BARRAGAN M.

International Symposium on Asynchronous Circuits and Systems

Venue: Snowbird (Utah), USA
Date: May 17-20, 2020

technical program committee : FESQUET L.

PhD thesis defenses

« Currently there is no defense planned »


Winner of PhD Forum at VLSI-SoC'2019 (Cuzco, PERU)

Award: Winner of PhD Forum at VLSI-SoC'2019 (27th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 6-9, 2019
Place: Cuzco (PERU)
Title: A Digital Event-Based Strategy for ASK demodulation
- Rodrigo IGA JADUE (TIMA - CDSI team)
- Sylvain ENGELS (TIMA - CDSI team)
- Laurent FESQUET (TIMA - CDSI team)


Best Paper Award at DDECS'2019 (Cluj Napoca, ROMANIA)

Award: Best Paper Award at DDECS'2019 (22nd International Symposium on Design and Diagnostics of Electronics Circuits and Systems)
Date : April 24-26, 2019
Place : Cluj Napoca (ROMANIA)
Title : "Encryption-Based Secure JTAG"
Authors :
- Emanuele VALEA (LIRMM, Montpellier)
- Mathieu DA SILVA (LIRMM, Montpellier)
- Marie-Lise FLOTTES (LIRMM, Montpellier)
- Giorgio DI NATALE (TIMA, AMfoRS team, Grenoble)
- Bruno ROUZEYRE (LIRMM, Montpellier)


IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Award: The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

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« Currently there is no job proposal. »