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2nd IEEE Federative Event on Design for Robustness

FEDfRo
Venue: Hotel Macedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Summary: Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications. Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security. These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), sponsored by the IEEE Council on Electronic Design Automation (CEDA), was initiated on 2016 to meet this goal by bringing together: - IOLTS: International Symposium on On-Line Testing and Robust System Design http://tima.imag.fr/conferences/iolts/iolts17/ a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems; - IMSTW: the International Mixed-Signal Testing Workshop http://tima.imag.fr/conferences/imstw/imstw17/ a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits;- - IVSW: the International Verification and Security Workshop http://tima.imag.fr/conferences/ivsw/ivsw17/ a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems. Starting from 2018, a fourth event, PATMOS, will also be part of FEDfRo. The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.

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PhD thesis defenses

« Native Simulation of MPSoC: Instrumentation and Modeling of NonFunctional Aspects ».

Candidate: O. Matoussi

Advisor: F. Pétrot

President of jury: F. Maraninchi

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: Le 30/11/2017 à 10 h 00, GRENOBLE INP (Viallet) - Amphi C

Abstract

Modern embedded systems are endowed with a high level of parallelism and significant processing capabilities as they integrate hundreds of cores on a single chip communicating through network on chip. The complexity of these systems and their dedicated software should not be an excuse for long design cycles, even though the design space is enormous and the underlying design decisions are critical. Thus, design space exploration, hardware/software coverification and performance estimation need to be conducted within a reasonable amount of time and early enough in the design process to avoid any tardy detection of functional or performance deficiencies. Cosimulation platforms are becoming an increasingly important part in design and verification steps. With instruction interpretationbased software simulation platforms being too slow as they model lowlevel details of the target system, an alternative software simulation approach known as native simulation or hostcompiled simulation has gained momentum this past decade. Native simulation consists of compiling the embedded software to the host binary format and executing it directly on the host machine. However, this technique fails to reflect the performance of the embedded software and its actual interaction with the target hardware. So, the speedup gained by native simulation comes at a price, which is the absence of nonfunctional information (such as time and energy) needed for estimating the performance of the entire system and ensuring its proper functioning. Without such information, native simulation approaches are limited to functional validation. Yielding accurate estimates entails the integration of highlevel abstract models that mimic the behavior of targetspecific microarchitectural components in the simulation platform and the accurate placement of the obtained nonfunctional information in the highlevel code. Backannotating nonfunctional information at the right place requires a mapping between the binary instructions and the highlevel code statements, which can be challenging particularly when compiler optimizations are enabled. In this thesis, we propose an annotation framework working at the compiler intermediate representation level to accurately annotate performance metrics extracted from the binary code, thanks to a dedicated mapping algorithm. This mapping algorithm is further enhanced to deal with aggressive compiler optimizations, such as loop unrolling, that radically alter the structure of the code. Our target architecture being a VLIW processor, we also model at a high level its instruction buffer to faithfully reproduce its timing behavior. The experiments we conducted to validate our mapping algorithm and component models yielded accurate results and high simulation speed compared to a cycle accurate ISS of the target platform.

 

« Testing Techniques for Detection of Hardware Trojans in Integrated Circuits of Trusted Systems ».

Candidate: L. Acunha Guimaraes

Advisor: L. Fesquet

President of jury: G. Gogniat

PhD: These de Doctorat, Université de Grenoble

Speciality: Nanoélectronique et Nanotechnologies

Defense: Le 01/12/2017 à 10 h 00, GRENOBLE INP - Amphi Gosse

Abstract

The world globalization has led the semiconductor industry to outsource design and fabrication phases, making integrated circuits (ICs) potentially more vulnerable to malicious modifications at design or fabrication time: the hardware Trojans (HTs). New efficient testing techniques are thus required to disclose potential slight and stealth HTs, and to ensure trusted devices. This thesis studies possible threats and proposes two new post-silicon testing techniques able to detect HTs implanted after the generation of the IC netlist. The first proposed technique exploits bulk built-in current sensors (BBICS) – which are originally designed to identify transient faults in ICs – by using them as testing mechanisms that provide statistically-comparable digital signatures of the devices under test. With only 16 IC samples, the testing technique can detect dopant-level Trojans of zero-area overhead.The second proposition is a non-intrusive technique for detection of gate-level HTs in asynchronous circuits. With this technique, neither additional hardware nor alterations on the original test set-up are required to detect Trojans smaller than 1% of the original circuit. The studies and techniques devised in this thesis contribute to reduce the IC vulnerability to HT, reusing testing mechanisms and keeping security features of original devices.

 

« Design flow for ultra-low power : nonuniform sampling and asynchronous circuits ».

Candidate: J. Simatic

Advisor: L. Fesquet

President of jury: F. Pétrot

PhD: These de Doctorat, Université de Grenoble

Speciality: Nanoélectronique et Nanotechnologies

Defense: Le 07/12/2017 à 10 h 00, GRENOBLE INP (Viallet) - Amphi Gosse

Abstract

Integrated systems are mainly heterogeneous systems with strong power consumption constraints. They embed actuators, sensors and signal processing units. To limit the energy consumption, they can exploit event-based techniques, namely non uniform sampling and asynchronous circuits. Indeed, they allow cutting drastically the amount of sampled data for many types of signals and reducing the system activity. To help designers in quickly developing platforms that exploit those event-based techniques, we elaborated a design framework called ALPS. It proposes an environment to determine and simulate at algorithmic level the sampling scheme and the associated processing in order to select the most efficient ones depending on the targeted application. ALPS generates directly the analog-to-digital converter based on the chosen sampling parameters. The elaboration of the processing unit uses a synchronous high-level synthesis tool and a desynchronization method that exploits specific asynchronous protocols to optimize the circuit area and power consumption. Finally, gate-level simulations allow analyzing and validating the energy consumption before continuing with a standard placement and routing flow. The conducted evaluations show a reduction factor of 3 to 8 of the consumption of the automatically generated circuits. The flow ALPS allow non-specialists to concentrate on the optimization of the sampling and the processing in function of their application and to reduce the circuit power consumptions by one to several orders of magnitude.

 

Awards


Runner-up Best Paper Award in SBCCI 2016 conference (Belo Horizonte, BRAZIL)

Project: Runner-up Best Paper Award in lnternational Symposium on Integrated Circuits and Systems Design (SBCCI) 2016

Project: New Asynchronous Protocols for Enhancing Area and Throughput in Bundled-Data Pipelines

Authors: Jean Simatic (TIMA, CDSI), Abdelkarim Cherkaoui (TIMA, CDSI), Rodrigo Possamai Bastos (TIMA, CDSI), and Laurent Fesquet (TIMA, CDSI)

Abstract: This paper presents two new area-reduced controllers for bundled-data asynchronous pipelines in which the stages have long critical paths. The proposed protocols allow to reduce the number of required delay elements by using the falling edge of the asynchronous request to indicate data validity. For critical path lengths of 25 gates, the first presented scheme decreases the controller area by 48% and slightly increases the maximum throughput (2%) in comparison to a standard micropipeline implementation. The other more-concurrent scheme proposition leads to a 25% area reduction and a 40% improvement of the maximum pipeline throughput.

August 29 - September 3, 2016

 

Best Presentation and Paper Award at JNRSE 2017 conference (Lyon, FRANCE)

Project: Best Presentation and Paper Award at JNRSE 2017 (7èmes Journées Nationales sur la Récupération et le Stockage d'Energie)

Title: "Modeling and operating temperature tuning of a thermally activated piezoelectric generator"

Authors: Adrian Rendon-Hernandez and Skandar Basrour

Abstract: This paper deals with the finite element model of a thermally activated piezoelectric generator. Furthermore, it presents an experimentally validated temperature tuning technique based on the gap distance of the triggering system. The working principle of proposed generator relies on the multi step thermal-to-mechanical-to-electrical energy conversion, overcoming inconveniences related to fast temporal temperatura variations and large temperature differences for efficient operating of classical direct thermal energy conversion. Performance optimization can be done in the form of temperature span tuning by changing the gap distance. By increasing this parameter, it is possible to maximize the Energy up to 10 times. Experimental data suggests that output energy up to 67 μW is possible when optimal gap distance is set. This corresponds to a power density of 103 μWcm-3

May 9-10, 2017

 

Best Paper Award, student 2nd place at NEWCAS 2017 conference (Strasbourg, FRANCE)

Project: Best Paper Award, student 2nd place at NEWCAS 2017

Title: On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept.

Authors: Assia El-hadbi (TIMA, CDSI), Abdelkarim Cherkaoui (TIMA, CDSI), Oussama Elissati (INPT, STRS), Jean Simatic (TIMA, CDSI) and Laurent Fesquet (TIMA, CDSI)

Abstract: A new fully digital high resolution time-to-digital converter (TDC) based on a self-timed ring oscillator (STR) is presented. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. The TDC has been implemented using 28 nm FDSOI technology to provide a proof of concept of the proposed method. Simulation results point out

June 25- 28, 2017

 

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