TIMA laboratory



IEEE International Test Conference

Venue: Phoenix (Arizona),
Date: October 28 - November 2, 2018

program committee : ANGHEL L., VATAJELU E.I.

Summary: It is our privilege to welcome you to the 49th International Test Conference (ITC) sponsored by IEEE and the IEEE Philadelphia Section. ITC is the world’s premier conference dedicated to electronics test. Our volunteer committees worked very hard to provide to you an exciting event with a balance of the latest research, practical applications, and networking opportunities. This year we are co-locating with ISTFA conference the week of October 28, 2018.

Our topics include emerging test needs for artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed-signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional and software-based test.

In addition to the usual best paper award, we have selected the top papers based on reviewers’ scores to be Distinguished Papers. These outstanding papers will be identified in the program.

ITC is expanding its presence! We had great success with our 2017 initial sister conferences, ITC-Asia and ITC-India in Taiwan and Bangalore, respectively.

The conference is organized in a way to provide you various methods to learn and discuss topics related to electronics test. Our keynote speakers are well known industry leaders and academic researchers that provide exciting insights. The technical papers are 20 minute presentations of papers that were selected from a rigorous review process with a few minutes for questions at the end of each paper. The exhibition floor consists of solutions providers who are available for discussion and learning about their offerings. A corporate forum is held on the exhibit floor where exhibiting companies present about their products. This year we plan to have one poster session held on the exhibition floor. Posters provide a very comfortable and informal environment to discuss details with the authors.

We recognize that networking is extremely valuable to our attendees. Multiple breaks and social events are integrated in the program to allow you to network with colleagues and other specialists. Free lunches are provided in the exhibit hall for full- and one-day ITC conference attendees.

On behalf of the 2018 International Test Conference steering committee, program committee and all the dedicated volunteers who are key to making the program complete, we welcome you to this year’s exciting technical program and exhibits.

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5th IEEE International Workshop on Test and Validation of High Speed Analog Circuits

Venue: Phoenix (Arizona),
Date: November 1-2, 2018

program chair : BARRAGAN M.

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14th International School on the Effects of Radiation on Embedded Systems for Space Applications

Venue: Noordwijk,
Date: November 12-16, 2018

co-general chair : VELAZCO R.

Summary: This five-day school SERESSA combines academic, government, and industrial communities working in the area of radiation effects on embedded systems. Radiation effects are a significant concern for space and avionics systems, as well as for critical applications operating at ground level such as automotive, medical or even banking.

During these fice days, lecturers with significant experience in key selected subjects will provide a complete state-of-the-art instruction in this strategic field. The school is based on lectures, exercises, and practical courses involving real case studies using the common tools of the domain.

The topics addressed cover the full spectrum of radiation effects on space-embedded systems: space environment, error mechanisms, testing, hardening by design, rate prediction. The intended audience includes both beginning and experienced researchers, engineers, and post-graduate students wishing to enhance their knowledge base in this rapidly evolving field.

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18th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications

Venue: Daytona Beach (Florida),
Date: December 4-7, 2018

technical program committee : BASROUR S.

Summary: Broadly speaking, PowerMEMS focuses on all aspects of energy conversion and processing at the micro and nano scales. Its topics of interest range from basic principles, to materials and fabrication, to devices and systems, to applications. All energy domains are of interest, including, but not limited to: electrical, fluidic, gravitational, hydraulic, mechanical, nuclear, optical, pneumatic and thermal energy domains.

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PhD thesis defenses

« Acceleration of memory accesses in dynamic binary translation ».

Candidate: A. Faravelon

Advisor: F. Pétrot

President of jury: F. Maraninchi

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: October 22nd, 2018 - 10:00, GRENOBLE INP (Viallet) - Amphi C


In this thesis we are interested in the acceleration of memory accesses in dynamic binary translation. For this, we base ourselves on methods whose main purpose is to manage the target’s address space with the host’s hardware. Two main methods for this have been explored, one based on hardware assisted virtualization, and the other on a Linux module. In the case of hardware assisted virtualization, we used the simulator as a specific guest. This one playing a role similar to that of an OS, in addition to its role of simulator, for the target. In particular, it is responsible for creating an enmbedded address space that can be used directly, without software simulation of an MMU. In the case of a method based on a Linux module, the same purpose is pursued. But the simulator continues to operate as a normal process. On the other hand, it now has a companion module, with which it can communicate through ioctl. This module is responsible for manipulating the host’s virtual memory management to create an embedded address space for the target. These methods have been implemented in Qemu and Linux and lead to significant performance gains.


« Requirement Driven automated tests for Cyber-physical Systems ».

Candidate: M. Chabot

Advisor: L. Pierre

President of jury: L. Du Bousquet

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: October 30th, 2018 - 14:00, GRENOBLE INP (Viallet) - Amphi Gosse


Nowadays, many major manufacturers in different fields are working towards the design of smart products to meet new market needs. The design of these systems is increasingly complex, as they are composed of many physical components controlled by applications running on processors. In order to support this multi-disciplinary design, the solution we propose in this thesis is to guide the system modeling and design by taking into account the test scenarios that will be used to validate its requirements. The method that we propose suggests reasoning at the system level and starting the design process by formalizing validation tests. In other words, it amounts to specifying the acceptance criterion(s) for the requirement as well as the test scenario necessary to verify it. Formalizing the tests in this way makes it possible to analyze the formulation of the requirements themselves and to remove any ambiguity. We propose a generic model of the structural view of the test infrastructure, and an associated UML profile. The behavioral view is modeled as SysML sequence diagrams. The test infrastructure interfaces provide testability constraints for the system to be designed. We have developed a tool, ARES (Automatic GeneRation of Executable Tests from SysML), which automatically transforms this structural/behavioral specification of the tests into simulatable or executable scenarios. These scenarios, analogous by construction, will be used to validate simulatable models of the system (Matlab/Simulink), then during the process of final verification of the product (with a TestStand environment). We present the application of this tool on various case studies associated with Schneider Electric products.



Best Paper Award at ETS'2018 (Bremen, GERMANY)

Project: Best Paper Award at ETS'2018 (23rd IEEE European Test Symposium)
Date: May 28 - June 01, 2018
Place: Bremen (GERMANY)
Title: "Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits"
Authors: Authors: Florent CILICI (TIMA-RMS), Manuel BARRAGAN (TIMA-RMS), Salvador MIR (TIMA-RMS), Estelle LAUGA-LARROZE (RFIC-Lab), Sylvain BOURDEL (RFIC-Lab)


Best Paper Award at SIGNAL'2018 (Nice, FRANCE)

Project: Best Paper Award at SIGNAL'2018 (3rd International Conference on Advances in Signal, Image and Video)
Date: May 20 - 24, 2018
Place: Nice (FRANCE)
Title: "Shaping Electromagnetic Emissions of Event-Driven Circuits Thanks to Genetic Algorithms"

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Best Paper Award at ASYNC'2018 (Vienna, AUSTRIA)

Project: Best Paper Award at ASYNC'2018 (24th IEEE International Symposium on Asynchronous Circuits and Systems)
Date: May 13-16, 2018
Place: Vienna (AUSTRIA)
Title: "Static Timing Analysis of Asynchronous Bundled-data Circuits"
Authors: Grégoire GIMENEZ (TIMA-CDSI), Abdelkarim CHERKAOUI (TIMA-CDSI), Guillaume COGNIARD, Laurent FESQUET (TIMA-CDSI)



Administrateur des systèmes d'information

Host: Service Informatique

Start Date: 01/10/2018

Duration: 18 mois

L'administrateur systèmes et réseaux du Laboratoire TIMA met en place, administre et exploite les moyens informatiques, matériels et logiciels, d'un laboratoire de 120 personnes. Il assure la sécurité, la disponibilité et l'évolution du réseau et des serveurs.
L’ingénieur devra après analyse de l’existant, proposer des axes d’amélioration. Il devra mettre en œuvre les solutions retenues et entreprendre la migration d’une partie de l’infrastructure dans des datacentres mutualisés.

• Etudier l'infrastructure, le réseau, les services actuels du laboratoire
• Etablir une cartographie du système d’informations et rédiger les documents nécessaires à son exploitation
• Proposer un plan de diminution, rationalisation, externalisation de services, afin d'en assurer la pérennité
• Garantir la sécurité du système d’information en appliquant les normes et standards de sécurité
• Procéder, après analyse, à la migration de services actuellement hébergés au laboratoire vers les Datacenter des tutelles
• Animer et coordonner l'activité d'une équipe de 2 techniciens et assurer le transfert de compétences
L’ensemble de ces actions se fera en partenariat avec les responsables systèmes et réseaux de l’INP, de l’UGA et du CNRS

Compétences générales :
• Connaissance approfondie des concepts et techniques d'architecture des systèmes et réseaux
• Connaissance des différentes architectures matérielles
• Savoir gérer les situations d'urgence et hiérarchiser les priorités
• Connaissance des technologies, protocoles et outils des systèmes et réseaux (il est entre autre nécessaire de maîtriser la notion de vlan et son application sous Linux)
• Connaissance générale des procédures de sécurité informatique (architecture réseau sécurisée, sécurisation des services)
• Etre en capacité de communiquer et d’expliquer ses choix notamment auprès de la direction et des utilisateurs et de dialoguer avec les ingénieurs systèmes et réseaux des différentes tutelles
• Lire couramment les notices techniques en anglais

Compétences spécifiques :
• Administrer les hyperviseurs (VMware) et les baies de stockage (isci)
• Utiliser des outils d'administration, d'audit et d'analyse des systèmes (logs système, nessus, nmap, snort)
• Maîtriser Linux (FAI, NFS, Kerberos, firewall, bridge, cryptsetup, ...)

See complete information to : Follow the link

Contact person: Frédéric PETROT et Anne-Laure FOURNERET