TIMA laboratory


Le prochain Conseil de Laboratoire aura lieu le

28/06/2019 à 09 h 00, Laboratoire TIMA - Salle T312, FRANCE


1st Workshop on Cybersecurity on Hardware

Venue: Canary Islands, SPAIN
Date: June 24-26, 2019

european projects chair : DI NATALE Giorgio, MAISTRI P., VATAJELU E.I.

Summary: The 1st edition of the NTMS Workshop on “CyberSECurity on HARDware (SecHard)”, will be a one day workshop that will be held in conjunction with the 10th IFIP International Conference on New Technologies, Mobility and Security (NTMS), from 24 to 26 June 2019 in Canary Islands – Spain.

Accepted and presented papers will be published in the conference proceedings and submitted to IEEE Xplore®, IFIP Digital Library as well as other Abstracting and Indexing (A&I) databases.

The conference & workshop are supported by IFIP TC6 WG6.2, IEEE COMSOC, IEEE SPAIN and IEEE Systems, Man and Cybernetics Society Spain.

Extended versions of selected best papers will be published in a special issue of the ISI indexed Euromicro/Elsevier journal “Microprocessors and Microsystems: Embedded Hardware Design” (MICPRO) having the 2017 Impact Factor as high as 1.049.

Areas of interest, in alphabetical order, include, but are not limited to:
- Architectures and Applications
- Attacks: Implementations and Countermeasures
- Constrained and Trusted Environments
- Cryptanalysis for Hardware
- Cryptographic Primitives
- Cyberphysical and Embedded Systems
- Energy Aware Hardware Implementations
- Evaluation & Testing
- Hardware Crypto-Processors
- Hardware Obfuscation
- Internet of Things (IoT) & Cybersecurity
- Lightweight Cryptography
- Networks, Protocols and Communications: Hardware Integrations
- Pervasive & Ubiquitous Computing, Privacy
- PUFs and TRNGs for Hardware
- Reconfigurable Cybersecurity Computing
- Reconfigurable Design & Implementation
- Reverse Engineering
- Smart Cards Cybersecurity
- System-on-Chip (SoC) Design & Implementation
- Trojans on Hardware
- Trust and Anti-Counterfeiting
- Vehicular Hardware Cybersecurity

7th Prague Embedded Systems Workshop

Venue: Prague, CZECH REP.
Date: June 27-29, 2019

european projects chair : DI NATALE Giorgio, VATAJELU E.I.

Summary: The Prague Embedded Systems Workshop is a research meeting intended for the presentation and discussion of students’ results and progress in all aspects of embedded systems design, testing and applications. It is organized by members of the Department of Digital Design at Faculty of Information Technology (which is the youngest) of the Czech Technical University in Prague (which is the oldest technical university in Central Europe). The workshop aims to enhance collaboration between different universities not only inside EU. It will be based on oral presentations, mutual communication and discussions.

A part of the PESW workshop is a contest of bachelor and master theses organized as a poster session and awarded by sponsors gifts. The main aim is a motivation for future Ph.D. studies.

25th IEEE International Symposium on On-Line Testing and Robust System Design

Venue: Rhodes Island, GREECE
Date: July 1-3, 2019

finance chair : ANGHEL L., VELAZCO R. general chair : NICOLAIDIS M. local organization : FOURNERET-ITIÉ A.-L., SIMEU E., ZERGAINOH N. - E. publication chair : PAPAVRAMIDOU P. steering committee member : NICOLAIDIS M. technical program committee : ANGHEL L., BARRAGAN M., BENABDENBI M., DI NATALE Giorgio, LEVEUGLE R., MIR S., NICOLAIDIS M., PAPAVRAMIDOU P., SIMEU E., VATAJELU E.I.

Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based.

The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2019 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

4th IEEE Federative Event on Design for Robustness

Venue: Rhodes Island, GREECE
Date: July 1-3, 2019

general chair : NICOLAIDIS M.

Summary: The pervasiveness of electronic systems in modern societies raises drastically the requirements to protect them against intentional attacks affecting security.

Nanometric scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; which are also worsening by the rapidly increasing complexity of modern SoCs. It is therefore mandatory mitigating these issues, for achieving acceptable levels of yield, reliability, and lifespan. Furthermore, these issues are making increasingly difficult meeting low power and high performance, which are paramount requirements in modern SoCs and numerous applications. Indeed:

- Extra circuitry used in fault mitigation architectures increases power;

- Supply voltage reduction (often used to reduce power), affects yield, reliability, and lifespan, as it reduces noise margins and increases therefore the sensitivity to soft-errors and EMI, and also increases circuit delays that increases the sensitivity to timing faults;

- Furthermore: Reducing supply voltage for reducing power affects performance as it increases circuit delays; Increasing clock frequency for increasing performance, affects yield, reliability, and lifespan, as it increases the sensitivity to timing faults and soft-errors, and it also affects power as it increases dynamic power and may also require increasing supply voltage for reducing circuit delays.

- Design for Timing is also further related with Design for Reliability, as in real time systems timing properties are as important as functional properties in delivering correct operation.

These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as Robustness-related DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Timing Performance, Design for Security, Design for Verification, …), and also as these techniques often weaken the goals of each other, it is often very difficult to guarantee that a design meets all its target specifications. Thus, it becomes mandatory to address all these techniques holistically in order to improve their global efficiency: achieve all the robustness requirements of each design, and moderate their cost. There is therefore a major need for a consolidated international forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), was initiated to meet this goal by bringing together:

- IOLTS: International Symposium on On-Line Testing and Robust System Design
a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems;

- PATMOS: International Symposium on Power and Timing Modeling, Optimization and Simulation
a well-established IEEE forum on Power and Timing Modeling, Optimization and Simulation.

- IVSW: the International Verification and Security Workshop
http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw19/ a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems.

These events are holding in the same location and are running in parallel. To encourage interactions, anyone registered in any of them can freely attend sessions of the other three events. All social activities are also done jointly for increasing interactions and technology cross-fertilization among attendees.

PhD thesis defenses

« Design flow and formal models for desynchronization of synchronous circuits ».

Candidate: Fra. Bertrand

Advisor: L. Fesquet

President of jury: P. Pannier

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Microélectronique

Defense: July 2nd, 2019 - 10:00, GRENOBLE INP (Viallet) - Amphi Gosse


In the smart-cards market, contactless communication becomes more and more common. In order to reduce the cost of the systems, the power budget available reduces along with the size reduction of the antenna. Many design techniques are available to improve the efficiency of digital design. However, asynchronous designs, because of their adaptability to variable operating conditions, offer a natural solution for the contactless power supply problematics. Nevertheless, the lack of engineers trained, and proven tools, to design asynchronous circuits brakes the adoption of asynchronous designs in the industry. To address theses issues, a systematic method allowing to turn already existing synchronous designs into asynchronous micropipelines had been developed. Using a formal model, a desynchronization process was established and used on a cryptographic module which was implemented on silicon. The characterization allowed us to evaluate the relevance of the desynchronization flow but also its limitations. The efficiency of desynchronized systems depending largely on the architecture of the initial synchronous circuit, the proposed method allows a quick estimation of the performances of the desynchronized circuit, and results in functional circuits.


« Built-In Self-Test solutions for high-performance and reliable analog, mixed-signal, and RF integrated circuits ».

Candidate: M. Barragan

Advisor: S. Mir

PhD: HDR, Université Grenoble Alpes

Speciality: Micro et Nano Electronique

Defense: July 9th, 2019 - 10:30, GRENOBLE INP (Viallet) - Amphi Gosse


The integration capabilities offered by current nanoscale CMOS technologies enable the fabrication of complete and very complex mixed-signal systems. However, manufacturing processes are prone to imperfections that may degrade –sometimes catastrophically– the intended functionality of the fabricated circuits. Extensive production tests are then needed in order to separate these defective or unreliable parts from functionally correct devices. Unfortunately, the co-integration of blocks of very distinct nature (analog, mixed-signal, digital, RF, ...) as well as the limited access to internal nodes in an integrated system make the test of these devices a very challenging and costly task.

BIST techniques have been proposed as a way to overcome these issues. These techniques aim at including some of the ATE functionality into the Device Under Test, in such a way that each fabricated system becomes self-testable. Applying BIST to the digital part of a complex integrated system is a common and standardized practice. Many test alternatives broadly proven in practice are available, all of them based on defect test and fault models. On the other hand, AMS-RF BIST techniques are still lagging behind due to the strict requirements imposed by the analog circuitry. Since AMS-RF circuits are usually tested by measuring their functional specifications, this means that each measurement has to comply with strict accuracy constraints to match the performance of the circuits under test.

A promising solution to these issues is the combination of BIST strategies and machine learning-based tests. Machine learning test strategies replace costly analog, mixed-signal and RF performance measurements by a set of simpler measurements that can be performed on-chip by low-cost built-in test circuitry. The core idea is to build a mapping model from a set of simple measurements to the set of functional specifications. However, this test strategy is not free of shortcomings either.

My research has been focused on overcoming the limitations of current BIST and machine learning-based test for complex AMS-RF circuits, with the final goal of providing innovative state-of-the-art test solutions for these complex systems



IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Award: The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

follow the link


Best Paper Award at ETS'2018 (Bremen, GERMANY)

Award: Best Paper Award at ETS'2018 (23rd IEEE European Test Symposium)
Date: May 28 - June 01, 2018
Place: Bremen (GERMANY)
Title: "Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits"
Authors: Authors: Florent CILICI (TIMA-RMS), Manuel BARRAGAN (TIMA-RMS), Salvador MIR (TIMA-RMS), Estelle LAUGA-LARROZE (RFIC-Lab), Sylvain BOURDEL (RFIC-Lab)


Best Paper Award at SIGNAL'2018 (Nice, FRANCE)

Award: Best Paper Award at SIGNAL'2018 (3rd International Conference on Advances in Signal, Image and Video)
Date: May 20 - 24, 2018
Place: Nice (FRANCE)
Title: "Shaping Electromagnetic Emissions of Event-Driven Circuits Thanks to Genetic Algorithms"

follow the link



« Currently there is no job proposal. »