TIMA laboratory

News


Le prochain Conseil Scientifique aura lieu le

21/09/2020 - de 09 h 00 à 11 h 30, Grenoble INP - Amphi Gosse, FRANCE


Conferences

28th IFIP/IEEE International Conference on Very Large Scale Integration

VLSI-SoC
Venue: Salt Lake City, USA
Date: October 5-7, 2020

steering committee member : MIR S.

4th International Conference on Control, Automation and Diagnosis

ICCAD (Control Automation and Diagnosis)
Venue: Paris, FRANCE
Date: October 7-9, 2020

industry liaison : SIMEU E. technical program committee : SIMEU E.

33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

DFT
Venue: Roma, ITALY
Date: October 19-21, 2020

technical program committee : ANGHEL L., DI NATALE Giorgio

Summary: DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

IEEE International Test Conference

ITC
Venue: Washington DC, USA
Date: November 3-5, 2020

steering committee member : DI NATALE Giorgio technical program committee : VATAJELU E.I.

Summary: International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

PhD thesis defenses

« 3D integrated circuit implementation of convolutional neural networks for embedded vision ».

Candidate: L. Fernandez-Brillet

Advisor: S. Mancini

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Micro et Nano Electronique

Defense: 28/09/2020 - 14:00, Grenoble INP - Amphi C

Abstract

The goal of this thesis is the efficient 3D integration of a convolutional neural network for specific real time applications with a limited power budget while maintaining the accuracy of these solutions as high as possible.

 

« Reliability Improvement by Dynamic Wearout Management using In-Situ Monitors ».

Candidate: R. Shah

Advisor: L. Anghel

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Micro et Nano Electronique

Defense: 05/10/2020 - 09:30, Grenoble INP - Amphi Gosse

Abstract

As technology node continues to shrink to achieve higher performance at high density, it has become extremely challenging to handle the effects of Process, Voltage, Temperature and Aging (PVTA) variations. The stringent requirement of achieving higher performance while maintaining the reliability of the design has become an important concern especially for the energy-efficient designs. The traditional approach of adding pessimistic timing margins to assure all operating points under worst case conditions is not feasible in advanced technology nodes due to the huge impact on design costs. In this thesis work, on-chip reliability and performance monitors as well as adaptive compensation techniques are investigated to address these challenges in the digital circuit design. Internally as well as externally situated monitors are evaluated for the accuracy of detection of PVTA variations. A novel externally situated timing monitor is proposed to detect PVTA variations accurately without impacting the timing closure of the reference design. A detailed analysis has been presented on the investigation of robustness of digital circuits using In-Situ Monitors emphasizing detection of global and local process variations, aging variations and cost impact of insertion of monitors on performance, power and area. For these analyses, measurements and simulation results are demonstrated using three different digital circuits implemented and fabricated in 28nm FDSOI CMOS technology of STMicroelectronics. Closed-loop adaptive voltage and body-bias compensation schemes have been proposed with In-Situ Monitors, and manufactured product results are analyzed.

 

Awards


Winner of PhD Forum at VLSI-SoC'2019 (Cuzco, PERU)

Award: Winner of PhD Forum at VLSI-SoC'2019 (27th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 6-9, 2019
Place: Cuzco (PERU)
Title: A Digital Event-Based Strategy for ASK demodulation
Authors:
- Rodrigo IGA JADUE (TIMA - CDSI team)
- Sylvain ENGELS (TIMA - CDSI team)
- Laurent FESQUET (TIMA - CDSI team)

 

Best Paper Award at DDECS'2019 (Cluj Napoca, ROMANIA)

Award: Best Paper Award at DDECS'2019 (22nd International Symposium on Design and Diagnostics of Electronics Circuits and Systems)
Date : April 24-26, 2019
Place : Cluj Napoca (ROMANIA)
Title : "Encryption-Based Secure JTAG"
Authors :
- Emanuele VALEA (LIRMM, Montpellier)
- Mathieu DA SILVA (LIRMM, Montpellier)
- Marie-Lise FLOTTES (LIRMM, Montpellier)
- Giorgio DI NATALE (TIMA, AMfoRS team, Grenoble)
- Bruno ROUZEYRE (LIRMM, Montpellier)

 

IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Award: The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

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