TIMA laboratory
News
L'anniversaire des 25 ans du Laboratoire TIMA aura lieu le
04/06/2018, Château de Sassenage, FRANCE
Evénement sur invitation
Cette journée est un moment fort dans la vie du Laboratoire.
Elle regroupera des anciens membres du Laboratoire, des industriels, des personnalités académiques et universitaires, collègues des autres laboratoires etc ...
Conferences
28rd International Workshop on Power And Timing Modeling, Optimization and Simulation
PATMOS
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018
Summary: PATMOS has a history of 30 years, being one of the first conferences focusing on low power. Starting 2018, PATMOS will be collocated with two complementary conferences, IOLTS and IVSW, forming FEDfRo, the federative event on Design for Robustness. The traditional scope of PATMOS has mainly been about the design of circuits and architectures optimized for highest performance at lowest power consumption. But meanwhile, power-efficiency has become extremely important for many more areas spreading far beyond this traditional R&D niche. Energy efficiency has become a must in the connected network of battery-operated nodes known as Internet-of-Things (IoT). Wearable devices, home appliances, vehicles and security surveillance systems mostly rely on small sensors that should ideally operate on battery charge for days or even weeks. However, current battery efficiencies do not keep up with the growing demands of IoT nodes for power, forcing us to seek novel techniques for energy harvesting and power optimization. Additionally, energy-efficient ICT (Information and Communication Technology) infrastructures are a key issue for local and global economies. Some predict that, if current trends continue, the electricity consumption caused by the Internet will increase up to 30 times in the year 2030. The strong increase of wireless communication and the growth of cloud computing require orders of magnitude more computational power.
PATMOS 2018 aims to find solutions for both, small-scaled integrated circuits in IoT nodes, and large-scale ICT infrastructures that require massive energy consumption.
3rd International Verification and Security Workshop
IVSW
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018
Summary: Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of security, verification, validation, test, and reliability to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. IVSW 2018 is sponsored by IEEE Council on Electronic Design Automation (CEDA).
24th IEEE International Symposium on On-Line Testing and Robust System Design
IOLTS
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018
Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based.
The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2018 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.
PhD thesis defenses
« New performance evaluation methods for early and refined software development on SoC platforms ».
Candidate: P. Njoyah Ntafam
Advisor: F. Pétrot
President of jury: F. Rousseau
PhD: These de Doctorat, Université de Grenoble
Defense: Le 20/04/2018 à 10 h 00, GRENOBLE INP (Viallet) - Amphi Gosse
Abstract
The thesis aims to identify, develop and experiment methods, based on models that will allow the performance estimation of embedded software on-chip (System-On-Chip, SoC), on early stage of a SoC project. In fact, current design methods, that are not running software, are no longer sufficient for the complexity of new architectures, composed of both multi-processors with cache coherence and dedicated subsystems. The challenge is to determine whether a combination of models can provide both the accuracy of required estimation, and simulation speed expected at the beginning of a SoC project, by hardware, system, and software architects.
« Optimization of the operation of a generator of memory hierarchies for embedded vision systems ».
Candidate: K. Hadj Salem
Advisor: S. Mancini
PhD: These de Doctorat, Université de Grenoble
Speciality: Micro et Nano Electronique
Defense: Le 26/04/2018 à 14 h 00, ESISAR - Amphi A042 (50 rue Barthélémy de Laffemas - BP 54 - 26902 VALENCE)
Abstract
The research of this thesis focuses on the application of the Operations Research (OR) methodology to design new optimization algorithms to enable low cost and efficient embedded vision systems, or more generally devices for multimedia applications such as signal and image processing. For the case of non-linear image accesses, one solution has been proposed by Mancini et al. (Proc. DATE 2012) in the form of a software tool, called Memory Management Optimization(MMOpt), that creates an ad-hoc memory hierarchies for such a treatment. It creates a circuit called a Tile Processing Unit (TPU) that contains the circuit for the treatment. In this context, we address the optimization challenge set by the efficient operation of the circuits produced by MMOpt to enhance the 3 main electronic design characteristics. They correspond to the energy consumption, performance and size/production cost of the circuit. This electronic problem is formalized as a 3-objective scheduling problem, which is called 3-objective Process Scheduling and Data Prefetching Problem (3-PSDPP), reflecting the 3 main electronic design characteristics under consideration. To the best of our knowledge, this problem has not been studied before in the OR literature. A review of the state of the art, including the previous work proposed by Mancini et al.(Proc.DATE, 2012) as well as a brief overview on related problems found in the OR literature, is then made. In addition, the complexity of some of the mono-objective sub-problems of 3-PSDPP problem is established. Several resolution approaches, including exact methods (ILP) and polynomial constructive heuristics, are then proposed. Finally, the performance of these methods is compared, on benchmarks available in the literature, as well as those provided by Mancini et al. (Proc.DATE, 2012), against the one currently in use in the MMOpt tool. The results show that our algorithms perform well in terms of computational efficiency and solution quality. They present a promising track to optimize the performance of the TPUs produced by MMOpt. However, since the user's needs of the MMOpt tool are contradictory, such as low cost, low energy and high performance, it is difficult to find a unique and optimal solution to optimize simultaneously the three criteria under consideration. A set of good compromise solutions between these three criteria was provided. The MMOpt's user can then choose the best compromise solution he wants or needs.
Awards
Best Poster at JNRDM'2017 (Strasbourg, FRANCE)
Project: Best Poster at JNRDM'2017 (Journées Nationales du Réseau Doctoral en Micro-nanoélectronique 2017)
Date: November 6-8, 2017
Place: Strasbourg (FRANCE)
Title: "Conception en vue du test d’un amplificateur de puissance à 60 GHz"
Authors: Florent CILICI, Manuel BARRAGAN, Estelle LAUGA-LARROZE, Sylvain BOURDEL, Salvador MIR
follow the link
Best Presentation and Paper Award at JNRSE'2017 (Lyon, FRANCE)
Project: Best Presentation and Paper Award at JNRSE 2017 (7èmes Journées Nationales sur la Récupération et le Stockage d'Energie)
Title: "Modeling and operating temperature tuning of a thermally activated piezoelectric generator"
Authors: Adrian RENDON-HERNANDEZ and Skandar BASROUR
Abstract: This paper deals with the finite element model of a thermally activated piezoelectric generator. Furthermore, it presents an experimentally validated temperature tuning technique based on the gap distance of the triggering system. The working principle of proposed generator relies on the multi step thermal-to-mechanical-to-electrical energy conversion, overcoming inconveniences related to fast temporal temperatura variations and large temperature differences for efficient operating of classical direct thermal energy conversion. Performance optimization can be done in the form of temperature span tuning by changing the gap distance. By increasing this parameter, it is possible to maximize the Energy up to 10 times. Experimental data suggests that output energy up to 67 μW is possible when optimal gap distance is set. This corresponds to a power density of 103 μWcm-3
May 9-10, 2017
Runner-up Best Paper Award in SBCCI'2016 (Belo Horizonte, BRAZIL)
Project: Runner-up Best Paper Award in lnternational Symposium on Integrated Circuits and Systems Design (SBCCI) 2016
Project: New Asynchronous Protocols for Enhancing Area and Throughput in Bundled-Data Pipelines
Authors: Jean SIMATIC (TIMA, CDSI), Abdelkarim CHERKAOUI (TIMA, CDSI), Rodrigo POSSAMAI-BASTOS (TIMA, CDSI) and Laurent FESQUET (TIMA, CDSI)
Abstract: This paper presents two new area-reduced controllers for bundled-data asynchronous pipelines in which the stages have long critical paths. The proposed protocols allow to reduce the number of required delay elements by using the falling edge of the asynchronous request to indicate data validity. For critical path lengths of 25 gates, the first presented scheme decreases the controller area by 48% and slightly increases the maximum throughput (2%) in comparison to a standard micropipeline implementation. The other more-concurrent scheme proposition leads to a 25% area reduction and a 40% improvement of the maximum pipeline throughput.
August 29 - September 3, 2016
