TIMA laboratory

PhD thesis defenses


« Native Simulation of MPSoC: Instrumentation and Modeling of NonFunctional Aspects ».

Candidate: O. Matoussi

Advisor: F. Pétrot

President of jury: F. Maraninchi

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: Le 30/11/2017 à 10 h 00 GRENOBLE INP (Viallet) - Amphi C

Abstract

Modern embedded systems are endowed with a high level of parallelism and significant processing capabilities as they integrate hundreds of cores on a single chip communicating through network on chip. The complexity of these systems and their dedicated software should not be an excuse for long design cycles, even though the design space is enormous and the underlying design decisions are critical. Thus, design space exploration, hardware/software coverification and performance estimation need to be conducted within a reasonable amount of time and early enough in the design process to avoid any tardy detection of functional or performance deficiencies. Cosimulation platforms are becoming an increasingly important part in design and verification steps. With instruction interpretationbased software simulation platforms being too slow as they model lowlevel details of the target system, an alternative software simulation approach known as native simulation or hostcompiled simulation has gained momentum this past decade. Native simulation consists of compiling the embedded software to the host binary format and executing it directly on the host machine. However, this technique fails to reflect the performance of the embedded software and its actual interaction with the target hardware. So, the speedup gained by native simulation comes at a price, which is the absence of nonfunctional information (such as time and energy) needed for estimating the performance of the entire system and ensuring its proper functioning. Without such information, native simulation approaches are limited to functional validation. Yielding accurate estimates entails the integration of highlevel abstract models that mimic the behavior of targetspecific microarchitectural components in the simulation platform and the accurate placement of the obtained nonfunctional information in the highlevel code. Backannotating nonfunctional information at the right place requires a mapping between the binary instructions and the highlevel code statements, which can be challenging particularly when compiler optimizations are enabled. In this thesis, we propose an annotation framework working at the compiler intermediate representation level to accurately annotate performance metrics extracted from the binary code, thanks to a dedicated mapping algorithm. This mapping algorithm is further enhanced to deal with aggressive compiler optimizations, such as loop unrolling, that radically alter the structure of the code. Our target architecture being a VLIW processor, we also model at a high level its instruction buffer to faithfully reproduce its timing behavior. The experiments we conducted to validate our mapping algorithm and component models yielded accurate results and high simulation speed compared to a cycle accurate ISS of the target platform.

 

« Testing Techniques for Detection of Hardware Trojans in Integrated Circuits of Trusted Systems ».

Candidate: L. Acunha Guimaraes

Advisor: L. Fesquet

President of jury: G. Gogniat

PhD: These de Doctorat, Université de Grenoble

Speciality: Nanoélectronique et Nanotechnologies

Defense: Le 01/12/2017 à 10 h 00 GRENOBLE INP - Amphi Gosse

Abstract

The world globalization has led the semiconductor industry to outsource design and fabrication phases, making integrated circuits (ICs) potentially more vulnerable to malicious modifications at design or fabrication time: the hardware Trojans (HTs). New efficient testing techniques are thus required to disclose potential slight and stealth HTs, and to ensure trusted devices. This thesis studies possible threats and proposes two new post-silicon testing techniques able to detect HTs implanted after the generation of the IC netlist. The first proposed technique exploits bulk built-in current sensors (BBICS) – which are originally designed to identify transient faults in ICs – by using them as testing mechanisms that provide statistically-comparable digital signatures of the devices under test. With only 16 IC samples, the testing technique can detect dopant-level Trojans of zero-area overhead.The second proposition is a non-intrusive technique for detection of gate-level HTs in asynchronous circuits. With this technique, neither additional hardware nor alterations on the original test set-up are required to detect Trojans smaller than 1% of the original circuit. The studies and techniques devised in this thesis contribute to reduce the IC vulnerability to HT, reusing testing mechanisms and keeping security features of original devices.

 

« Design flow for ultra-low power : nonuniform sampling and asynchronous circuits ».

Candidate: J. Simatic

Advisor: L. Fesquet

President of jury: F. Pétrot

PhD: These de Doctorat, Université de Grenoble

Speciality: Nanoélectronique et Nanotechnologies

Defense: Le 07/12/2017 à 10 h 00 GRENOBLE INP (Viallet) - Amphi Gosse

Abstract

Integrated systems are mainly heterogeneous systems with strong power consumption constraints. They embed actuators, sensors and signal processing units. To limit the energy consumption, they can exploit event-based techniques, namely non uniform sampling and asynchronous circuits. Indeed, they allow cutting drastically the amount of sampled data for many types of signals and reducing the system activity. To help designers in quickly developing platforms that exploit those event-based techniques, we elaborated a design framework called ALPS. It proposes an environment to determine and simulate at algorithmic level the sampling scheme and the associated processing in order to select the most efficient ones depending on the targeted application. ALPS generates directly the analog-to-digital converter based on the chosen sampling parameters. The elaboration of the processing unit uses a synchronous high-level synthesis tool and a desynchronization method that exploits specific asynchronous protocols to optimize the circuit area and power consumption. Finally, gate-level simulations allow analyzing and validating the energy consumption before continuing with a standard placement and routing flow. The conducted evaluations show a reduction factor of 3 to 8 of the consumption of the automatically generated circuits. The flow ALPS allow non-specialists to concentrate on the optimization of the sampling and the processing in function of their application and to reduce the circuit power consumptions by one to several orders of magnitude.