TIMA laboratory

PhD thesis defenses


« Acceleration of memory accesses in dynamic binary translation ».

Candidate: A. Faravelon

Advisor: F. Pétrot

President of jury: F. Maraninchi

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: October 22nd, 2018 - 10:00 GRENOBLE INP (Viallet) - Amphi C

Abstract

In this thesis we are interested in the acceleration of memory accesses in dynamic binary translation. For this, we base ourselves on methods whose main purpose is to manage the target’s address space with the host’s hardware. Two main methods for this have been explored, one based on hardware assisted virtualization, and the other on a Linux module. In the case of hardware assisted virtualization, we used the simulator as a specific guest. This one playing a role similar to that of an OS, in addition to its role of simulator, for the target. In particular, it is responsible for creating an enmbedded address space that can be used directly, without software simulation of an MMU. In the case of a method based on a Linux module, the same purpose is pursued. But the simulator continues to operate as a normal process. On the other hand, it now has a companion module, with which it can communicate through ioctl. This module is responsible for manipulating the host’s virtual memory management to create an embedded address space for the target. These methods have been implemented in Qemu and Linux and lead to significant performance gains.

 

« Requirement Driven automated tests for Cyber-physical Systems ».

Candidate: M. Chabot

Advisor: L. Pierre

President of jury: L. Du Bousquet

PhD: These de Doctorat, Université de Grenoble

Speciality: informatique

Defense: October 30th, 2018 - 14:00 GRENOBLE INP (Viallet) - Amphi Gosse

Abstract

Nowadays, many major manufacturers in different fields are working towards the design of smart products to meet new market needs. The design of these systems is increasingly complex, as they are composed of many physical components controlled by applications running on processors. In order to support this multi-disciplinary design, the solution we propose in this thesis is to guide the system modeling and design by taking into account the test scenarios that will be used to validate its requirements. The method that we propose suggests reasoning at the system level and starting the design process by formalizing validation tests. In other words, it amounts to specifying the acceptance criterion(s) for the requirement as well as the test scenario necessary to verify it. Formalizing the tests in this way makes it possible to analyze the formulation of the requirements themselves and to remove any ambiguity. We propose a generic model of the structural view of the test infrastructure, and an associated UML profile. The behavioral view is modeled as SysML sequence diagrams. The test infrastructure interfaces provide testability constraints for the system to be designed. We have developed a tool, ARES (Automatic GeneRation of Executable Tests from SysML), which automatically transforms this structural/behavioral specification of the tests into simulatable or executable scenarios. These scenarios, analogous by construction, will be used to validate simulatable models of the system (Matlab/Simulink), then during the process of final verification of the product (with a TestStand environment). We present the application of this tool on various case studies associated with Schneider Electric products.