TIMA laboratory

PhD thesis defenses


« Convolutional Neural Networks for embedded vision ».

Candidate: L. Fernandez-Brillet

Advisor: S. Mancini

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Informatique

Defense: 28/09/2020 - 14:00 Grenoble INP - Amphi C

Abstract

Convolutional Neural Networks (CNNs) are currently the state of the art solution to most Computer Visionproblems. In this sense, embedded systems - specially image sensors - can greatly benefit from being able tolocally perform this kind of processing. However, the computational complexity of such solutions makes this a verychallenging task. Through this thesis, multiple techniques allowing to ease the computational complexity of CNNswill be proposed. These techniques will then be applied to an applicative object detection scenario in order todesign a very efficient face detection solution, which is then evaluated in an embedded multiprocessor.

 

« Reliability Improvement by Dynamic Wearout Management using In-Situ Monitors ».

Candidate: R. Shah

Advisor: L. Anghel

PhD: These de Doctorat, Université Grenoble Alpes

Speciality: Micro et Nano Electronique

Defense: 05/10/2020 - 09:30 Grenoble INP - Amphi Gosse

Abstract

As technology node continues to shrink to achieve higher performance at high density, it has become extremely challenging to handle the effects of Process, Voltage, Temperature and Aging (PVTA) variations. The stringent requirement of achieving higher performance while maintaining the reliability of the design has become an important concern especially for the energy-efficient designs. The traditional approach of adding pessimistic timing margins to assure all operating points under worst case conditions is not feasible in advanced technology nodes due to the huge impact on design costs. In this thesis work, on-chip reliability and performance monitors as well as adaptive compensation techniques are investigated to address these challenges in the digital circuit design. Internally as well as externally situated monitors are evaluated for the accuracy of detection of PVTA variations. A novel externally situated timing monitor is proposed to detect PVTA variations accurately without impacting the timing closure of the reference design. A detailed analysis has been presented on the investigation of robustness of digital circuits using In-Situ Monitors emphasizing detection of global and local process variations, aging variations and cost impact of insertion of monitors on performance, power and area. For these analyses, measurements and simulation results are demonstrated using three different digital circuits implemented and fabricated in 28nm FDSOI CMOS technology of STMicroelectronics. Closed-loop adaptive voltage and body-bias compensation schemes have been proposed with In-Situ Monitors, and manufactured product results are analyzed.