System Level Synthesis

Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

PETROT Frederic

Last publications

Vivet P., Thonnard Y., Lemaire R., Santos Cr., Beigné E., Bernard Ch., Darve F., Lattard D., Miro-Panades I., Dutoit D., Clermidy F., Cheramy S., Sheibanyrad H., Pétrot F., Flamand E., Michailos J., Arriordaz A., Wang L., Schloeffel J., A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links, IEEE Journal of Solid State Circuits, Vol. 52, No. 1, pp. 33-49, DOI: 10.1109/JSSC.2016.2611497, 2017
Cunha M., Matoussi O., Pétrot F., Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms, Journal on Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 16, No. 2, pp. 30:1-30:21, DOI: 10.1145/2990193, 2017
Michel L., Pétrot F., Dynamic Binary Translation of VLIW Codes on Scalar Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 789-800, DOI: 10.1109/TCAD.2016.2604294, 2017
Bel Hadj Amor H., Sheibanyrad H., Pétrot F., A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'17), pp. 200-205, Bochum, GERMANY, DOI: 10.1109/ISVLSI.2017.43, 2017
Alemdar H., Leroy V., Prost-Boucle A., Pétrot F., Ternary neural networks for resource-efficient AI applications, 2017 International Joint Conference on Neural Networks (IJCNN'17), pp. 2547-2554, Anchorage, AK, UNITED STATES, DOI: 10.1109/IJCNN.2017.7966166, 2017
Annual activity report