System Level Synthesis
since 1994

Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

PETROT Frédéric

Last publications

Muller O., Prost-Boucle A., Bourge A., Pétrot F., Efficient Decompression of Binary Encoded Balanced Ternary Sequences (Early Access), Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2019.2906678, 2019
Fernandez-Mesa B.J., Andrade Porras L.-L., Pétrot F., Electronic System Level Design of Heterogeneous Systems: a Motor Speed Control System Case Study, IEEE International New Circuits and Systems Conference (NEWCAS 2019), Munich, GERMANY, 2019
Brignon E., Pierre L., Assertion-Based Verification through Binary Instrumentation, Design, Automation and Test in Europe (DATE'2019), Florence, ITALY, 2019
Rousseau F., Muller O., Conception des systèmes VLSI, Techniques de l'Ingénieur, Vol. E 2 455 / Base documentaire : TIB276DUO, 2018
Prost-Boucle A., Bourge A., Pétrot F., High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression, ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Ed. ACM IEEE, Vol. 31, No. 3, pp. Article No. 15, DOI: 10.1145/3270764, 2018
Annual activity report