System Level Synthesis
since 1994

Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

PETROT Frederic

Last publications

Hadj Salem K., Optimization of the operation of a generator of memory hierarchies for embedded vision systems, These de Doctorat, 2018
Njoyah Ntafam P., New performance evaluation methods for early and refined software development on SoC platforms, These de Doctorat, 2018
France-Pillois M., Martin J., Rousseau F., Optimization of the GNU OpenMP Synchronization Barrier in MPSoC, International Conference of Architecture of Computing Systems (ARCS'2018), pp. 57-69, Braunschweig, GERMANY, DOI:, 2018
Hadj Salem K., Kieffer Y., Mancini S., Meeting the Challenges of Optimized Memory Management in Embedded Vision Systems Using Operations Research, Recent Advances in Computational Optimization, Results of the Workshop on Computational Optimization WCO 2016, Fidanova, Stefka (Eds.) , Ed. Springer , pp. 177-205, Vol. 717, 2018
Dumas J., Dynamic sharing set for scalable cache coherence protocols, These de Doctorat, 2017
Annual activity report