Research

SLS

System Level Synthesis
since 1994


Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

PETROT Frederic

Last publications

Dumas J., Dynamic sharing set for scalable cache coherence protocols, These de Doctorat, 2017
 
Matoussi O., Native Simulation of MPSoC: Instrumentation and Modeling of NonFunctional Aspects, These de Doctorat, 2017
 
Bernard M., Modular processing system for emission tomography with CdZnTe detector, These de Doctorat, 2017
 
Bel Hadj Amor H., Memory hierarchy in embedded multiprocessor system built around networks on chip, These de Doctorat, 2017
 
Vivet P., Thonnard Y., Lemaire R., Santos Cr., Beigné E., Bernard Ch., Darve F., Lattard D., Miro-Panades I., Dutoit D., Clermidy F., Cheramy S., Sheibanyrad H., Pétrot F., Flamand E., Michailos J., Arriordaz A., Wang L., Schloeffel J., A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links, IEEE Journal of Solid State Circuits, Vol. 52, No. 1, pp. 33-49, DOI: 10.1109/JSSC.2016.2611497, 2017
 
Annual activity report