Research

RIS

Robust Integrated Systems
since 2015


Research topics

photo RIS

RIS addresses the fundamental challenges induced by aggressive nanometric scaling, including: high defect densities caused by increasing process, voltage and temperature variations, accelerated aging, EMI and soft errors; as well as stringent power constraints imposed by fast increasing power densities and temperatures, and battery-life requirements in mobile applications.
To address these challenges, the RIS group works at multiple levels of system architecture for developing robust design approaches (and tools for their qualification), including: circuit, bloc, microarchitecture, array-level, and software. Our goals are multiple, and concern the development and use of self-healing and self-adapting approaches for: mitigating fabrication faults (in particular those induced by process variations), to improve fabrication yield; mitigating field failures (in particular those induced by aging) to increase product lifetime, as well as those induced by voltage and temperature variations, EMI and soft errors to improve reliability; operating the circuits at aggressively low voltage levels to aggressively reduce power.

Team leader

VELAZCO Raoul

Last publications

Charif A., Coelho A., Ebrahimi M., Bagherzadeh N., Zergainoh N.-E., First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip, IEEE Transactions on Computers, Ed. IEEE, Vol. , pp. 1-14, DOI: 10.1109/TC.2018.2822269, 2018
 
Bonnoit T., Zergainoh N.-E., Nicolaidis M., Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance, IEEE Transactions on VLSI Systems, Ed. IEEE, Vol. , pp. 1-14, DOI: 10.1109/TVLSI.2018.2818021, 2018
 
Ramos P., Vargas V., Baylac M., Zergainoh N.-E., Velazco R., SEE error-rate evaluation of an application implemented in COTS Multi/Many-core processors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. , DOI: 10.1109/TNS.2018.2838526, 2018
 
Kchaou A., El Hadj Youssef W., Velazco R., Tourki R., An exhaustive analysis of SEU effects in the SRAM memory of soft processor, International Journal of Engineering Science and Technology, Vol. 13, No. 1, 2018
 
Coelho A., Charif A., Zergainoh N.-E., Fraire J., Velazco R., A soft-error resilient route computation unit for 3D Networks-on-Chips, Design, Automation & Test in Europe (DATE'2018), Dresden, GERMANY, 2018
 
Annual activity report