Robust Integrated Systems
since 2015

Research topics

photo RIS

RIS addresses the fundamental challenges induced by aggressive nanometric scaling, including: high defect densities caused by increasing process, voltage and temperature variations, accelerated aging, EMI and soft errors; as well as stringent power constraints imposed by fast increasing power densities and temperatures, and battery-life requirements in mobile applications.
To address these challenges, the RIS group works at multiple levels of system architecture for developing robust design approaches (and tools for their qualification), including: circuit, bloc, microarchitecture, array-level, and software. Our goals are multiple, and concern the development and use of self-healing and self-adapting approaches for: mitigating fabrication faults (in particular those induced by process variations), to improve fabrication yield; mitigating field failures (in particular those induced by aging) to increase product lifetime, as well as those induced by voltage and temperature variations, EMI and soft errors to improve reliability; operating the circuits at aggressively low voltage levels to aggressively reduce power.

Team leader


Last publications

Kchaou A., El Hadj Youssef W., Velazco R., Tourki R., An exhaustive analysis of SEU effects in the SRAM memory of soft processor, International Journal of Engineering Science and Technology, Vol. 13, No. 1, 2018
Clemente J.A., Fraire J., Solinas M., Franco F., Villa F., Rey S., Baylac M., Puchner H., Mecha H., Velazco R., SEU Sensitivity SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2 MeV Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. , 2018
Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chip, Journal of VLSI Design, Ed. Hindawi Publishing Corporation, Vol. , DOI: 10.1155/2017/9427678, 2017
Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips, IEEE Transactions on Emerging Topics in Computing, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TETC.2017.2776909, 2017
Charif A., Design, Parallel Simulation and Implementation of High-Performance Fault-Tolerant Networks-on-Chip Architectures, These de Doctorat, 2017
Annual activity report