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Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design

Author(s): F. Rousseau, S. Meftali, F. Gharsalli, A. A. Jerraya

ISRN: TIMA--RR-02/04-03--FR

In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components. The concept of wrapper allows automatic adaptation of physical interfaces to a communication network. We give also a generic architecture to produce this wrapper, either for processors or for other specific components such as memory or IP. This approach has successfully been applied on a lowlevel image processing application.