Publications
Free tools
Free tools
- Static Timing Analysis of Bundled-Data Circuits
(Equipe : CDSI)
The Local Clock Set method provides the asynchronous community with an efficient method to perform the Static Timing Analysis of bundled-data circuits using standard clocked EDA tools.
For the community to benefit from the capacities of this methodology and to build scalable and robust asynchronous design flows, different bundled-data scheme implementations and associated LCS rules have been made available and can be freely downloaded.
Information on the LCS methodology can be found in :
- Static timing analysis of asynchronous bundled-data circuits by G. Gimenez, A. Cherkaoui, G. Cogniard and L. Fesquet
- From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits (to be published) by G. Gimenez, J. Simatic and L. Fesquet
Don't hesitate to contact Laurent Fesquet (laurent [.] fesquet [@] univ-grenoble-alpes [.] fr) for more information.
site
- AMfoRS' TIMA Emulation-based Fault Injection plaTform on Virtex-5
(Equipe : AMfoRS)
See URL link for more information
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- VSYML
(Equipe : VDS)
VSYML stands for VHDL Symbolic Simulator in CAML. It is an automated application to extract VHDL design models. The high-level symbolic simulation algorithm that is implemented in VSYML is described in an article published in the Proceedings of the Design and Diagnostics of Electronic Circuits and Systems (DDECS 2009): High-level symbolic simulation for automatic model extraction by F. Ouchet, D. Borrione, K. Morin-Allory and L. Pierre.VSYML is open-source software and may freely be downloaded here.
News:
The change log is available here.
2010-04-06 VSYML 1.7 is released (with support for blackbox functions).
2009-05-15 VSYML 1.6 is released (with basic support for VHDL 2008).
2009-04-09 VSYML 1.5 is released.
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