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C-VHDL co-simulation for functional validation of embedded software

Author(s): F. Nacabal, C. Valderrama, F. Hessel, P. Paulin, A. A. Jerraya

Journal: Technique et Science Informatiques (TSI)

Volume: 19

Issue: 8

Pages: 1097-126

Recent sub-micron circuit integration technologies enabled the gathering on only one chip of the whole set of components of complex systems. In addition, flexibility requirements force us to increase the programmability of these components, which makes the embedding of processors inevitable. Associated with these processors, the embedded software needs a particular design flow, focuses on a deepened validation before realization of the system. This article present an approach based on C-VHDL co-simulation making it possible to validate the functionality of the software embedded in its real hardware environment, without requiring a processor model. The relevant use of this method in the industrial production of a complex videophone system shows the utility of the co-simulation.