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Synthesis of Dependency-aware Traffic Gererators from NoC Simulation Traces

Author(s): O. Alcantara, V. Fresse, F. Rousseau, H. Sheibanyrad

Journal: Journal of Systems Architecture (JSA)

Volume: 71

Pages: 102-113

Doi : 10.1016/j.sysarc.2016.10.004

Networks-on-chip (NoCs) are currently the most appropriate communication infrastructure for many-core embedded systems. As NoCs become a de facto standard for on-chip systems, traffic generation models become critical for system-on-chip (SoC) design. Traditional trace-based traffic distorts the injection rate and the effects of congestion due to the lack of packets dependency information. They also have large data storage requirements. In this paper, we propose a new framework to process traces generated by message passing applications modeled as acyclic task graphs. This framework builds dependency-aware traffic generators (DATGs) by retrieving the packet dependencies from traces in a single simulation. The DATGs accurately replace the application nodes in emulations or simulations to explore the NoC design space. Our experimental analysis showed that our framework is more accurate than trace-based simulation for a broad range of NoC configurations. Moreover, our proposed framework uses only 3% of the data storage required by the traces.