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A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio Sigma-Delta ADC

Author(s): M. Barragan, R. Alhakim, H. Stratigopoulos, M. Dubois, S. Mir, H. Le Gall, N. Bhargava, A. Bal

Journal: IEEE Transactions on Circuits and Systems

Volume: 63

Issue: 11

Pages: 1876-1888

Doi : 10.1109/TCSI.2016.2602387

This paper proposes a fully-digital BIST architecture for the dynamic test of Sigma Delta ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the Sigma Delta modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio Sigma Delta ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1 per cent and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.