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Evaluation of analog/RF test measurements at the design stage

Author(s): H. Stratigopoulos, S. Mir, A. Bounceur

Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume: 28

Issue: 4

Pages: 582-590

Doi : 10.1109/TCAD.2009.2016136

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.