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Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Author(s): I. Moussa, Z. Sugar, R. Suescun, M. Diaz-Nava, M. Pavesi, S. Crudo, L. Gazzi, A. A. Jerraya

Doc. Source: Design Automation Conference (DAC'99)

Publisher: IEEE

Pages: 598-603

Doi : 10.1145/309847.310006

This paper describes the experience and the lessons learned during the design of an ATM traffic shaper circuit using behavioral synthesis. The experiment is based on the comparison of the results of two parallel design flows starting from the same specification. The first used a classical design method based on RTL synthesis. The second design flow is based on behavioral synthesis. The experiment has shown that behavioral synthesis is able to produce efficient design in terms of gate count and timing while bringing a threefold reduction in design effort when compared to the RTL design methodology.