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Harmonic cancellation strategies for on-chip sinusoidal signal generation using digital resources

Author(s): H. Malloug, M. Barragan, S. Mir, H. Le Gall

Doc. Source: International Mixed-Signal Testing Workshop (IMSTW 2017)

Publisher: IEEE

Doi : 10.1109/IMS3TW.2017.7995201

Harmonic cancellation strategies have been pro- posed as a promising solution for the implementation of accu- rate on-chip sinusoidal signal generators while minimizing the required on-chip resources. Harmonic cancellation-based genera- tors can be implemented using digital resources to provide a set of phase-shifted digital square-wave signals and a summing network built with passive or active components for scaling and combining these phase-shifted signals. The practical implementation of the scaling weight ratios for the different phased-shifted signals is a critical aspect of the harmonic cancellation strategy. Indeed, small variations between these weights due to mismatch and process variations will reduce the effectiveness of the technique and increase the magnitude of undesired harmonic components. In this work, different harmonic cancellation strategies are presented and analyzed with the goal of simplifying the on- chip implementation of the scaling weight s. Stati stical behavioral simulations are provided in order to demonstrate the feasibility of the proposed approach.