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HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic

Author(s): S. Pontié, A. Bourge, A. Prost-Boucle, P. Maistri, O. Muller, R. Leveugle, F. Rousseau

Doc. Source: Euromicro/IEEE Conference on Digital System Design (DSD'16)

Publisher: IEEE

Pages: 511-518

Doi : 10.1109/DSD.2016.51

High-Level Synthesis (HLS) is used by hardware developers to achieve higher abstraction in circuit descriptions. In order to shorten the hardware development time via HLS, we present an adjustment of the Iterative and Incremental Design(IID) methodology, frequently used in software development. In particular, our methodology is relevant for the development of applications with unusual complexity: the method was applied here to the development of large modular arithmetic, commonly used for cryptography applications (e.g., Elliptic Curves). Rapid feedback on circuit characteristics is used to evaluate deep architectural changes in short time, greatly reducing the time-to-market with respect to hand-made designs. In addition, our approach is highly flexible, since the same generic high-level description can be used to produce an entire set of circuits, each with different area/performance trade-offs. Thanks to the proposed approach, any change to the initial specification (e.g., the curve used) is also very fast, while it may require a large effort in the case of hand-made designs.