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Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs

Author(s): G. Plassan, H.J. Peter, K. Morin-Allory, F. Rahim, S. Sarwary, D. Borrione

Doc. Source: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16)

Publisher: IEEE

Pages: 1-6

We propose a novel semi-automatic methodology to formally verify clock-domain synchronization protocols in industrial-scale hardware designs. Establishing the functional correctness of all clock-domain crossings (CDCs) is crucial in every system-on-chip (SoC) assembly flow. While other semi-automatic approaches require non-trivial manual deductive reasoning, our approach produces a small sequence of easy queries to the user. We use counterexample-guided abstraction refinement (CEGAR) as the algorithmic back-end, and the user influences the course of the algorithm based on information extracted from intermediate abstract counterexamples. The workload on the user is small, both in terms of number of queries and the degree of design insight to provide. With this approach, we formally proved the correctness of every CDC in a recent SoC design from STMicroelectronics comprising over 300,000 registers and seven million gates.