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Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator

Author(s): A. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M. Barragan, S. Mir

Doc. Source: 21st IEEE European Test Symposium (ETS'16)

Publisher: IEEE

This paper presents a self-testable BIST applica- tion for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18 m CMOS process is presented here as demonstrator. Transistor-level simu- lation results with a 2Vpp sin! usoidal test-stimulus show an effec- tive resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.