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Methodological Framework for NoC Resources Dimensioning on FPGAs

Author(s): V. Fresse, C. Combes, M. Payet, F. Rousseau

Doc. Source: International Workshop on Design and Performance of Networks on Chip (DPNoC'15)

The two main challenges involved in prototyping a SoC (System-On-Chip) on a FPGA (field programmable gate array) are optimal tuning of the communication architecture according to the task graph of an application, and dimensioning the FPGA resources. In this paper, we present a methodological framework to estimate the number of resources required for a given communication architecture and task graph. Data analysis was based on a set of synthesized results for a given on-chip network. The most appropriate models were identified using a data mining approach. The evaluation of the models shows that the relative error is less than 5% in most cases. It is therefore possible to estimate the required resources in a short exploration time, without the synthesis steps.