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Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology

Author(s): M. Saliva, F. Cacho, C. Ndiaye, V. Huard, D. Angot, A. Bravaix, L. Anghel

Doc. Source: IEEE International Reliability Physics Symposium (IRPS'15)

Publisher: IEEE

Pages: CA.4.1 - CA.4.6

Doi : 10.1109/IRPS.2015.7112782

For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Then Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.