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On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

Author(s): G. Renaud, M. Barragan, S. Mir

Doc. Source: 23rd IEEE Asian Test Symposium (ATS'14)

Publisher: IEEE

Pages: 212-217

Doi : 10.1109/ATS.2014.47

Linearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators.