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Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces

Author(s): S. Lagraa, A. Termier, F. Pétrot

Doc. Source: Best Paper Award in Design Automation and Test in Europe (DATE'14)

Publisher: IEEE

Pages: 1-6

Doi : 10.7873/DATE.2014.199

Nowadays, a challenge faced by many developers is the profiling of parallel applications so that they can scale over more and more cores. This is especially critical for embedded systems powered by Multi-Processor System-on-Chip (MPSoC), where ever demanding applications have to run smoothly on numerous cores, each with modest power budget. The reasons for the lack of scalability of parallel applications are numerous, and it can be time consuming for a developer to pinpoint the correct one. In this paper, we propose a fully automatic method which detects the instructions of the code which lead to a lack of scalability. The method is based on data mining techniques exploiting low level execution traces produced by MPSoC simulators. Our experiments show the accuracy of the proposed technique on five different kinds of applications, and how the information reported can be exploited by application developers.