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A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies

Author(s): M. Bahmani, H. Sheibanyrad, F. Pétrot, F. Dubois, P. Durante

Doc. Source: IEEE Computer Society Annual Symposium on VLSI (ISVLSI'12)

Publisher: IEEE

Pages: 9-14

Doi : 10.1109/ISVLSI.2012.19

In this paper, we detail the design and implementation of a router for vertically-partially-connected 3D-NoCs based on stacked 2D-meshes. This router implements the necessary hardware to support a recently introduced routing algorithm called "Elevator-First", which targets topologies with irregularly placed vertical connections in a deadlock free manner, using only two virtual channels in the plane. The micro-architectural design shows that the proposed router requires few additional hardware. Our studies about the practicality of the algorithm and its router implementation demonstrate that it has low overhead compared to a router for fully connected 3D-NoCs. Using ST Microelectronics 65nm CMOS technology Elevator-First router with 7 ports has a total area of 0.07mm², an Operating frequency of over 3GHz and a power consumption of around 3mW.