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Ternary Stimulus for Fully Digital Dynamic Testing of SC ΣΔ ADCs

Author(s): M. Dubois, H. Stratigopoulos, S. Mir

Doc. Source: IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW'12)

Publisher: IEEE

Pages: 5 - 10

Doi : 10.1109/IMS3TW.2012.12

In this paper, a ternary stimulus is proposed for testing $Sigma Delta$ SD Analog-to-Digital Converters (ADCs). The ternary stimulus is composed of three logic levels {-1,0,1} and is obtained by adding a binary stream with a delayed version of itself. Only four switches are added to the input stage of the modulator of the $Sigma Delta$ ADC for facilitating the injection of the ternary stimulus. Compared to a binary stimulus, the ternary stimulus contains less quantization noise and allows measuring the SNDR of the $Sigma Delta$ ADC for the whole input dynamic range. We discuss the optimization of the ternary stimulus and we demonstrate its efficiency using behavioral simulations of a second-order switched-capacitor (SC) $Sigma Delta$ modulator.