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Non-regular 3D mesh Networks-on-Chip

Author(s): V. Pasca, L. Anghel, C. Rusu, M. Benabdenbi

Doc. Source: DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)

Stacked 3D integration emerged as a key technology for high performance and low power tera-scale computation. It consists in stacking multiple layers of active silicon, possibly in different technologies (i.e. digital, analog, RF, MEMS, etc.), connected with vertical wires called Thru-Silicon-Vias (TSVs). The main benefits of 3D integration rely on the fact that the long intra-die global wires (~mm) are replaced by TSVs with significantly reduced lengths (~ tens of µm). 3D technologies cumulate the intra-die and inter-die defects and parametric faults. Thus, the interconnect yield is significantly reduced. 3D networks-on-chip (NoCs) are the interconnect fabrics on which the Intellectual Property (IP) blocks of 3D systems communicate. In this paper, non-regular D NoCs are proposed. They consist in stacked 2D mesh networks that are connected by inter-die links. The stacked networks are not necessary identical and they reflect the non-uniform distribution of the system’s IP blocks. In each layer, only master nodes have ports for inter-die (up and/or down) communication. Non-master nodes communicate with the upper and lower layers through master-up and master-down nodes, respectively. The zone on influence (ZOI) of a master node consists in the routing nodes that use it for inter-die communication.