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Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs

Author(s): Q. Meunier, F. Pétrot

Doc. Source: Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09)

Publisher: IEEE

Pages: 432 - 435

The evolution of the consumer electronic devices leads to a consolidation of the architectures towards fairly homogeneous multiprocessor platforms. As these highly programmable architectures execute explicitly parallel programs, and until automatic parallel compilers exist, the software programmer has to expose thread (i.e. coarse grain) level parallelism to use these resources. Thread is currently a well accepted programming paradigm which relies on locks, provided by some means by the hardware, to ensure atomicity of accesses. Unfortunately, programs written with locks are hard to design and debug. A decade ago, the idea of Transactional Memories was introduced to replace locks in order to simplify programming. This paper reviews the hardware issues related to Hardware Transactional Memories and proposes some directions for the design and implementation of such systems.