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Evaluation of a BIST technique for CMOS imagers

Author(s): L. Lizarraga, S. Mir, G. Sicard

Doc. Source: IEEE Asian Test Symposium (ATS’07)

Publisher: IEEE

Pages: 378-383

This paper evaluates a new Built-In-Self-Test (BIST) technique for CMOS imagers. The test stimuli are based on applying electrical pulses at the pixel photodiode anode in order to carry out a purely electrical test. The aim of this work is to eliminate some, if not all, optical tests of the pixel matrix to reduce time and cost during production testing at a wafer level. The quality of the BIST technique is evaluated by computing test metrics such as fault coverage for catastrophic and single parametric faults, and pixel fault acceptance and fault rejection under process deviations for two different pixel architectures.