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On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures

Author(s): F. Pétrot, A. Greiner, P. Gomez

Doc. Source: 10th Euromicro conference on Digital System Design (DSD’06)

Publisher: IEEE

Pages: 53-60

Doi : 10.1109/DSD.2006.73

The concept of network on chip (NoC) is a recent breakthrough in the system on chip (SoC) design area. A lot of work has been done to define efficient NoC architectures and implementations. In this paper, our goal is twofold. Firstly, we want to outline that the use of a NoC based sharedmemory multiprocessor SoC challenges the application integrator because of the underlying assumptions of software, namely cache coherency and memory consistency. These problems are well known in general purpose shared memory multiprocessors. However, when designing a SoC, we benefit on the one hand from the knowledge of the applications, the much simpler usage of virtual memory, lower interconnect latencies and very high bandwidth at lost cost, but on the other hand we suffer from more tight design constraints (yield, power, predictable performances, ...). Secondly, we define simple and yet attractive solutions -in term of design time and hardware cost- to both problems in the context of application specific multiprocessor SoCs.