PhD Thesis

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« System-level synthesis and hardware/software codesign ».

Author: T. Ben Ismail
Advisor: A.-A. Jerraya
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Informatique
Defense: January 09 1996
Pages: 213


The objective of this thesis is to develop a system-level specification and synthesis approach that allows an interactive hardware/software codesign of applications onto multiprocessor architectures composed of ASICs, FPGAs, or software processors. This thesis presents a hardware/software codesign methodology that starts with a specification given in the system-level description language, called SDL, and generates, through an intermediate representation called Solar, hardware and software descriptions in VHDL and C languages respectively. Two main steps are required in order to transform this specification into mixed hardware/software descriptions used for synthesising the hardware and compiling the software parts. Firstly, a system-level partitioning step is needed in order to transform, and split the model into a set of communicating subsystems. Secondly, a communication synthesis step, including protocol selection and interface generation tasks, is needed in order to refine the model into a set of interconnected subsystems. Each of these subsystems is described either in C code or in VHDL. Software parts may be compiled for a standard microprocessor and hardware parts may feed existing high-level synthesis tools in order to programme FPGAs or design ASICs.

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