PhD Thesis

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« System level specification and communication synthesis for hardware/software co-design ».

Author: J.- M. Daveau
Advisor: A.-A. Jerraya
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Microélectronique
Defense: December 19 1997
Pages: 192


As the system complexity grows there is a need for new methods to handle large system design. One way to manage that complexity is to rise the level of abstraction of the specifications by using system level description languages. On the other side, as the level of abstraction rise the gap between the concepts used for the specification at the system level (communication channels, interacting processes, data types) and those used for hardware synthesis becomes wider. Although these languages are well suited for the specification and validation of complex real time distributed systems, the concepts manipulated are not easy to map onto hardware description languages. It is thus necessary to defines methods for system level synthesis enabling efficient synthesis from system level specifications. The subject of this thesis is the presentation of a new approach of generation of C and VHDL code from system level specifications in SDL. This approach solves the main problem encountered by previous approach : inter process communications. SDL communication can be translated in VHDL for synthesis. This is achieved by the use of a powerful intermediate form that support the modelling for synthesis of a wide range of communication schemes. This intermediate form allows to apply to the system a set of transformations in order to obtain the desired solution. The main refinement step, called communication synthesis is aimed at fixing the protocol and interface used by the different processes to communicate. The refined specification can be translated in C and VHDL and synthesised by commercial tools. We illustrate the feasibility of this approach through an application to a telecommunication example : the TCP/IP over ATM protocol.

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