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« Global validation method for system on chip ».

Author: F. Hunsinger
Advisor: A.-A. Jerraya
Co-advisor: S. Francois
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Micro et Nano Electronique
Defense: March 06 2006
ISBN: ISBN: 2-84813-084-9
Pages: 150

Abstract

Actual technologies facilitate integration of many components onto a single chip. These systems called system on chip (SoC) are a heterogeneous assembly of hardware and software components. As quality and time to market constraints of SoCs increase, validation becomes the key point (70% of the overall design process). Verification of the integration is done through simulation and consists to check component functionalities and interconnections in the system. It is often achieved by executing software programs on the embedded processors. Programs are generally designed at low level (assembly, C) which makes difficult to design complex test scenarios that need sophisticated synchronisation schemes. Furthermore, their use does not enable performing the complete system validation. The main contributions of this work for accelerating validation are: (1) the definition of a validation methodology using different verification techniques targeting specific SoC issues; (2) the definition of a new verification method of the integration based on high level software test programs using an operating system. This method was validated on an industrial SoC aimed at high definition television applications.

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