PhD Thesis

< back to PhD thesis

« Embedded software modeling at different abstraction levels for validation and synthesis of system-on-chips ».

Author: A. Bouchhima
Advisor: A.-A. Jerraya
Co-advisor: F. Pétrot
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Micro et Nano Electronique
Defense: May 06 2006
ISBN: ISBN: 2-84813-089-X
Pages: 153


Exploring and validating architectural choices related both to hardware platform design and embedded software is a key enabler to reach a convenient performance/cost tradeoff. By analysing classic design flows, it turns out that the major source behind such developpment cost is due to the late integration of hardware and software parts of a multiprocessor system-on-chip (MPSoC) system. In this thesis, we address this problem of late integration by proposing a unified model allowing the joint representation, at different abstraction levels, of the hardware/software architecture. This model is aimed at easing the gradual SoC design while allowing the validation and the evaluation of the resulted performance at each abstraction level. the contributions of this thesis are (1) the definition of a unified representation model of hardware/software architectures at different abstraction levels, (2) the specification of an execution semantic of this unified model in the context of a global cosimulation environment based on SystemC and (3) a methodology for the automatic refinement of these abstract interfaces relying on a composition technology based on the service dependecy graph.

pdf pdf

Other localisation