PhD Thesis

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« Design of secure and very low power circuits : an asynchronous alternative ».

Author: G. Gimenez
Advisor: L. Fesquet
President of jury: L. Torres
thesis reviewer(s): O. Sentieys, S. Guilley,
thesis examinator(s): M. Renaudin,
These de Doctorat Université Grenoble Alpes
Speciality: Micro et Nano Electronique
Defense: February 12 2021


Microelectronics industry has always been confronted with the twofold challenge of reducing costs and improving performances. But the 3rd digital revolution and the emergence of the "everyone, everything, everywhere, everytime connected" have subversively redefined the challenges this industry faces. Consumption and security are issues that were once limited to very specific applications, but which are now gaining in importance and constraining the majority of integrated circuits. For years, Moore’s law and Dennard’s scale have observed a continuous increase in the number of operations per unit of energy, yet these are running out of steam and physical and economic limits seem to prevail. Moreover, these two issues are very often opposed, and security is generally only achieved at the expense of additional consumption. In this manuscript we propose to study an alternative based on so-called asynchronous (or clockless) logic. We show that the main a priori with respect to these circuits – their design complexity – can be circumvented using standard CAD tools, making them an accessible solution for synchronous designers. We also show that these circuits can be used to build high-performance security primitives – PUF and TRNG. We study their flaws and propose adapted countermeasures. Finally, without preaching a radical change towards self-sequencing circuits, we argue for a progressive integration of asynchronous logic, starting by circuits with low-power and security concerns.

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