PhD Thesis

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« Performance evaluation for heterogeneous MPSoC design ».

Author: I. Bacivarov
Advisor: A.-A. Jerraya
These de Doctorat Grenoble INP
Speciality: Micro et Nano Electronique
Defense: June 28 2006
ISBN: ISBN: 2-84813-090-3
Pages: 194


Multi-processor system-on-chip (MPSoC) is a concept that aims at integrating multiple subsystems on a single chip. Systems that put together complex HW and SW subsystems are difficult to analyze and even harder to optimize. Performance evaluation is a key step in any design, allowing for decisions and trade-offs, in view of overall system optimization. The literature shows that a large part of the design time spent in performance evaluation, and iterations become prohibitive in complex designs. Therefore, the challenge of building high-performance MPSoCs is closely related to the availability of fast and accurate performance evaluation methods. In our work, “performance” is restricted to time related performances of the final architecture. The timing aspect is intensively analyzed for the validation of real-time systems and the optimization of interconnect subsystems. We are also concerned with the speed of any proposed performance evaluation method, as evaluation times may become prohibitive for complex MPSoC designs. Our main objective is to define a global performance evaluation methodology for MPSoC. We also orient our research towards software performance modeling, maintaining a high level of abstraction, in order to have a high evaluation speed, and including timing annotations, in order to have good evaluation

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