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PhD Thesis


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« Modeling and Simulating the Effects of Laser Fault Injection on ICs ».

Author: R. Andreoni Camponogara Viera
Advisor: P. Maurine
Co-advisor: R. Possamai Bastos, J.-M. Dutertre
President of jury: B. Rouzeyre
thesis reviewer(s): J.-M. Portal, J.-L. Danger,
thesis examinator(s): G. Cathebras,
These de Doctorat Université de Montpellier
Speciality: Systèmes Automatiques et Microélectroniques
Defense: October 02 2018

Abstract

Laser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of CMOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR drop that contributes to the fault injection process. This paper describes our research on the assessment of this contribution. It shows by simulation and experiments that during laser fault injection campaigns, laser-induced IR drop is always present when considering circuits designed in deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that allows the use of the model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor as large as 2.4 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems.

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