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« Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability (confidential thesis) ».

Author: A. Sivadasan
Advisor: L. Anghel
Co-advisor: V. Huard
President of jury: I. O'Connor
thesis reviewer(s): M. Sonza-Reorda, J.-M. Portal,
These de Doctorat Université Grenoble Alpes
Speciality: Microélectronique
Defense: June 29 2018
ISBN: 978-2-11-129242-0

Abstract

Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus providing a better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on aging of standard cells and digital circuits with time, under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using body-biasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology.