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« Native Simulation of MPSoC: Instrumentation and Modeling of NonFunctional Aspects ».

Author: O. Matoussi
Advisor: F. Pétrot
President of jury: F. Maraninchi
thesis reviewer(s): Fr. Pecheux, C. Rochange,
thesis examinator(s): B. Dupont De Dinechin , Abdoulaye Gamatié,
These de Doctorat Université Grenoble Alpes
Speciality: informatique
Defense: November 30 2017
ISBN: 978-2-11-129233-8

Abstract

Modern embedded systems are endowed with a high level of parallelism and significant processing capabilities as they integrate hundreds of cores on a single chip communicating through network on chip. The complexity of these systems and their dedicated software should not be an excuse for long design cycles, even though the design space is enormous and the underlying design decisions are critical. Thus, design space exploration, hardware/software coverification and performance estimation need to be conducted within a reasonable amount of time and early enough in the design process to avoid any tardy detection of functional or performance deficiencies. Cosimulation platforms are becoming an increasingly important part in design and verification steps. With instruction interpretationbased software simulation platforms being too slow as they model lowlevel details of the target system, an alternative software simulation approach known as native simulation or hostcompiled simulation has gained momentum this past decade. Native simulation consists of compiling the embedded software to the host binary format and executing it directly on the host machine. However, this technique fails to reflect the performance of the embedded software and its actual interaction with the target hardware. So, the speedup gained by native simulation comes at a price, which is the absence of nonfunctional information (such as time and energy) needed for estimating the performance of the entire system and ensuring its proper functioning. Without such information, native simulation approaches are limited to functional validation. Yielding accurate estimates entails the integration of highlevel abstract models that mimic the behavior of targetspecific microarchitectural components in the simulation platform and the accurate placement of the obtained nonfunctional information in the highlevel code. Backannotating nonfunctional information at the right place requires a mapping between the binary instructions and the highlevel code statements, which can be challenging particularly when compiler optimizations are enabled. In this thesis, we propose an annotation framework working at the compiler intermediate representation level to accurately annotate performance metrics extracted from the binary code, thanks to a dedicated mapping algorithm. This mapping algorithm is further enhanced to deal with aggressive compiler optimizations, such as loop unrolling, that radically alter the structure of the code. Our target architecture being a VLIW processor, we also model at a high level its instruction buffer to faithfully reproduce its timing behavior. The experiments we conducted to validate our mapping algorithm and component models yielded accurate results and high simulation speed compared to a cycle accurate ISS of the target platform.

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