PhD Thesis

< back to PhD thesis

« Moniteurs de Vieillissement in-situ: Méthodologie d’intégration et application à la gestion dynamique de la fiabilité ».

Author: A. Benhassain
Advisor: L. Anghel
Co-advisor: F. Cacho
thesis reviewer(s): G. Di Natale, C. Maneux,
thesis examinator(s): M. Nicolaidis, O. Heron,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: May 29 2017
ISBN: 978-2-11-129225-3


Increasing performance demands in advanced technology, together with limited energy budgets, force integrate circuit designers to think about new ways of saving power. One innovative way of doing so is presented in this work. The newly developed Adaptive Voltage Scaling (AVS) scheme tunes the supply voltage of digital circuits according to the present Process, Voltage and Temperature variations as well as Aging (PVTA). The key components of the proposed approach are in-situ delay monitors, detecting late but still nonerroneous signal transitions (pre-errors). Based on the measured pre-error rate, the voltage is adjusted with a low-overhead control unit connected to the on-chip voltage regulator. This way power consumption is optimized, by exploiting unused timing margin, produced by state-of-the-art worst-case designs. This work has been done in STMicroelectronics and has been developed over four chapters in order to integrate reliability progressively from devices to digital circuits: in the first chapter we are interested in technological developments that have been necessary from standard CMOS technologies (40LP, 28LP) to FDSOI technology for 28nm node as well as monotonic degradation mechanisms such as BTI and HCI. Then, the impact of these degradation mechanisms along with PVT on datapath timing is discussed. The second chapter summarizes the state-of-arts of in-situ monitors and shows the characterization results of three kinds of pre-error in-situ monitors. The third chapter looks first at the integration of in-situ monitor in the digital implementation flow. As a second step, a potential critical path selection algorithm is developed. This algorithm is based on sub-critical paths identified by Static Timing Analysis (STA) before and after aging. The fourth chapter exhibits the experimental results of digital circuits that contain in-situ monitors. These circuits are designed in 45nm, 28LP and 28FDSOI technology and tested under different PVTs along with workload conditions. The results demonstrate the robustness of in-situ monitor to cope with different kinds of variations. Also, the behavior of in-monitor using AVS scheme is shown.

pdf pdf