PhD Thesis

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« Memory hierarchy in embedded multiprocessor system built around networks on chip ».

Author: H. Bel Hadj Amor
Advisor: F. Pétrot
Co-advisor: A. Sheibanyrad
President of jury: S. Niar
thesis reviewer(s): J-P. Diguet , D. Etiemble,
thesis examinator(s): Q. Meunier,
These de Doctorat Université Grenoble Alpes
Speciality: Informatique
Defense: October 05 2017
ISBN: 978-2-11-129231-4


Multi/many-cores parallel systems for high-power computing at low energy costs are nowadays a reality. However, exploiting the performance of these architectures depends on the efficiency of the system in managing data accesses. The aim of our work is to improve the efficiency of these accesses by exploiting the hardware architecture characteristics. In a first part, we propose a new cache hierarchy organization that aims at maximizing the use of the available storage space at each level. This solution, based on non-uniform cache access architectures (NUCA), supports inter and intra-level transfers of the hierarchy. It requires a cache coherency protocol that suits its specifications. Obviously, the transfer of data in the hierarchy is also a determinant of the system performance. In a second part, we consider the specific communication needs of the protocol. We suggest the use of a virtualized network as an ad-hoc communication medium to manage consistency traffic at a lower cost. It links the caches of the same level to support intra-level transfers, which are a specificity of our protocol, in order to reduce the average access latency.

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