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PhD Thesis


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« Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors ».

Author: V. Vargas
Advisor: R. Velazco
President of jury: F. Pétrot
thesis reviewer(s): L. Giraud, O. Romain,
thesis examinator(s): N.- E. Zergainoh,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: April 28 2017
ISBN: 978-2-11-129227-7

Abstract

The large computing capacity, great flexibility, low-power consumption, intrinsic redundancy and high performance provided by multi/many-core processors make them ideal to overcome with the new challenges in computing systems. However, the degree of scale integration of these devices increases their sensitivity to the effects of natural radiation. Consequently manufacturers, industrial and university partners are working together to improve their characteristics which allow their usage in critical embedded domains. In this context, the work done throughout this thesis aims at evaluating the impact of SEEs on parallel applications running on multi-core and many-core processors, and proposing a software approach to improve the system reliability called NMR-MPar. The methodology used for evaluation was based on multiple-case studies and their analysis. The different scenarios implemented consider a wide range of system configurations in terms of multi-processing mode, programming model, memory model, and resources used. For the experimentation, two COTS devices were selected: the Freescale PowerPC P2041 quad-core built in 45nm SOI technology, and the KALRAY MPPA-256 many-core processor built in 28nm CMOS technology. The case-studies were evaluated through fault-injection and neutron radiation testing. The obtained results serve as useful guidelines to developers for choosing the most reliable system configuration according to their requirements. Furthermore, the evaluation results of the proposed NMR-MPar fault-tolerant approach based on redundancy and partitioning criteria boost the usage of COTS multi/many-core processors in high-level dependability systems

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