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PhD Thesis


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« Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors ».

Author: P. Ramos
Advisor: R. Velazco
President of jury: A. Sylvestre
thesis reviewer(s): L. Naviner, P. Benoit,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: April 18 2017
ISBN: 978-2-11-129226-0

Abstract

The present thesis proposes a general and affordable error-rate prediction approach for evaluating the sensitivity of applications implemented in multi and many-core processors exposed to harsh radiation environments. To validate the generality of this approach, three different COTS devices were targeted aiming at representing the most relevant technological and architectural aspects of multi/many-core processors. The first one was the Freescale P2041 quad-core processor manufactured in 45nm SOI technology which implements ECC and parity in their cache memories. The second one was the Adapteva Epiphany E16G301 microprocessor manufactured in 65nm CMOS process which integrates 16 processor cores and do not implement any protection mechanism. The third one was the Kalray MPPA-256 many-core processor manufactured in 28nm TSMC CMOS technology which integrates 16 compute clusters each one with 17 processor cores, and implements ECC in its static memories and parity in its cache memories. The SEE sensitivity evaluation and the error-rate prediction was accomplished by combining radiation experiments with 14 Mev neutrons in particle accelerators to emulate a harsh radiation environment, and fault injection in cache memories, shared memories or processor registers, to simulate the consequences of SEUs in the execution of the program. A deep analysis of the observed errors was carried out to identify vulnerabilities in the protection mechanisms. Critical zones such as address tag and general purpose registers were mainly affected during the radiation experiments.

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