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« Design and development of low-power and reliable logic circuits based on spin-transfer torque magnetic tunnel junctions ».

Author: E. Deng
Advisor: L. Anghel
Co-advisor: G. Prenat
President of jury: J.-M. Portal
thesis reviewer(s): I. O'Connor, L. Torres,
thesis examinator(s): J.-O. Klein,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: February 10 2017
ISBN: 978-2-11-129224-6

Abstract

Spintronics devices, such as spin transfer torque based magnetic tunnel junction (STT-MTJ), are under intensive investigation to overcome the static power issue caused by the shrinking of CMOS technology. Hybrid logic-in-memory (LIM) architecture allows reducing latency and dynamic power due to long data traffic. This thesis focuses on the design of hybrid MTJ/CMOS logic circuits and memories. By using a compact STT-MTJ model and the STMicroelectronics CMOS design kit, we design and optimize the single-bit and multi-bit hybrid MTJ/CMOS circuits. Magnetic random access memory (MRAM) based on the multi-context hybrid MTJ/CMOS structure is proposed. Then, based on the LIM concept, non-volatile logic/arithmetic circuits are designed and analyzed including NOT, AND, OR, XOR and full-adder (FA). Furthermore, we optimize the FA from the circuit-, structure- and device-level. Finally, LIM-based non-volatile content addressable memory (CAM) and magnetic decoders are designed.

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