PhD Thesis

< back to PhD thesis

« Design of an analog-digital converter based on a piecewise linear ramp for image sensor with calibration techniques ».

Author: C. Pastorelli
Advisor: S. Mir
Co-advisor: P. Mellot
thesis reviewer(s): G. N. Lu, L. Latorre,
thesis examinator(s): G. Sicard, P. Magnan,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: December 15 2016
ISBN: 978-2-11-129222-2


The aim of this thesis is the implementation of new image sensors for mobile in CMOS (Complementary Metal Oxide Semiconductor) technology to meet strong market demand. Next generations of products require image sensors with high performances. These improvements would change the image quality with low noise architecture in one hand, and the use of new technologies to increase the signal level, or reduce the power consumption in the other hand. The gain in image quality leads to increase the size of the pixel’s array, and the resolution of the data -the conversion speed becoming critical-. The subject of this thesis focuses on improving this latter point. A comparative study has been made between several architectures to find the best solution that would fit our needs. The ramp converter is the most suitable for small pixels, but his main drawback is the conversion time that requires 2N clock cycles. To obtain a higher frame rate, a method taking advantage of the photon noise has been presented. This readout circuit is based on a piecewise linear ramp converter and an algorithm that allows the linearization of the data. Furthermore, for noise reduction, the new architecture must take into account the digital correlated double sampling. During the period of design, test modes have also been designed and implemented to allow characterization of the circuit. The innovative part is the use of a piecewise linear ramp, which in simulation, reduces the readout time of 1us per row. However, this element needs calibration. A CMOS image sensor prototype of 13Mpixel has been made in 65 nm, 5 levels of metals, and 1 level of poly standard CMOS technology. Measurements showed that the INL and DNL of the converter were as good as with a conventional linear ramp. A careful consideration has been given to the measurement of noise, which unfortunately is higher than a "conventional" sensor. However, the consumption remains the same while having a faster conversion speed. The solutions are simple to integrate structurally and easy to implement. They have the advantage of not affecting the surface of the pixel, thus preserve the performance of the latter. The results found from the silicon-on measures are very encouraging, we gain almost 20% of the conversion time.

pdf pdf